Miller Clamp Circuit for WBG Gate Spike and Oscillation Suppression
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Solution Overview
Problem
Wide bandgap high voltage power devices face issues with false turn-on and gate-loop oscillation due to parasitic inductances, which existing Miller clamping circuits cannot fully address, and using negative OFF-state gate voltage increases reverse-conduction loss and risks gate overstress.
Innovation Solution
A Miller clamping circuit using a low voltage GaN HEMT to achieve both Miller clamping and negative gate voltage spike clamping, allowing for single-polarity gate driving with a 0 V gate turn-off voltage, thereby suppressing false turn-on and protecting the gate from overstress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Miller clamping circuit is used to suppress crosstalk-induced gate spikes, then false turn-on due to positive gate spikes is suppressed, but gate-loop oscillation and reduced switching speed cannot be addressed
Solution Approach 1:
The gate driver circuit integrates multiple functions into a single device: Miller clamping to suppress positive gate spikes, negative gate voltage spike suppression, and gate-loop oscillation damping. This multi-functional approach allows the circuit to address all three parasitic inductance issues simultaneously, eliminating the need for separate circuits for each problem.
Solution Approach 2:
The patent combines the Miller clamp function with negative gate voltage spike suppression and oscillation damping capabilities into a unified gate driver circuit. By merging these functions, the circuit achieves comprehensive protection against all parasitic inductance effects while maintaining simple circuit topology and avoiding the need for multiple separate components.
2Reliability
If negative OFF-state gate voltage is used to suppress false turn-on, then gate voltage spikes and oscillation-induced false turn-on are suppressed, but reverse-conduction loss increases and gate overstress risk occurs
Solution Approach 1:
The circuit applies preliminary anti-action by preparing the Miller clamp and negative spike suppression mechanisms in advance to counteract gate voltage spikes before they cause false turn-on. The circuit proactively clamps voltage excursions both positive and negative, eliminating the need for continuous negative gate bias and thereby avoiding increased reverse-conduction loss.
Solution Approach 2:
The patent converts the harmful effect of parasitic inductance-induced gate voltage spikes into a beneficial clamping action. By using the Miller clamp circuit to detect and immediately suppress both positive and negative gate voltage excursions, the circuit transforms potential harmful voltage spikes into controlled clamping events that protect against false turn-on without requiring continuous negative gate bias, thus avoiding increased reverse-conduction loss.
3Productivity
If parasitic inductance is present in the gate loop, then switching speed decreases and switching loss increases, but adding clamping circuits increases circuit complexity
Solution Approach 1:
The gate driver circuit is designed with multi-functionality to simultaneously provide Miller clamping, negative spike suppression, and oscillation damping without requiring separate dedicated circuits for each function. This integrated approach maintains simple circuit topology while achieving comprehensive protection, thereby avoiding increased circuit complexity despite the presence of parasitic inductance.
Solution Approach 2:
The patent merges multiple protection functions into a single unified gate driver circuit, combining Miller clamp, negative voltage suppression, and oscillation damping capabilities. This consolidation eliminates the need for additional separate clamping circuits, maintaining simple circuit architecture while effectively addressing all parasitic inductance issues and preserving high switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses false turn-on and gate-loop oscillation, reduces switching loss, and minimizes reverse-conduction loss while ensuring safe gate operation, all without the complexity of dual-polarity driving.
Implementation Method 1
a first diode having an anode connected to a ground terminal of a driver IC chip; and a cathode connected to a control terminal of the semiconductor switching device; a first resistor connected in parallel with the first diode
Implementation Method 2
a second diode having an anode connected to the low side terminal of the semiconductor switching device and a cathode connected to a second end of the second resistor
Implementation Method 3
A Miller clamping circuit using a low voltage GaN HEMT to achieve both Miller clamping and negative gate voltage spike clamping
Data Source
AI summary
A Miller clamping circuit for driving a wide bandgap (WBG) device is provided. The Miller clamping circuit comprises: a semiconductor switching device having high side terminal connected to gate of the WBG device; and low side terminal connected to source of the WBG device; a first diode having anode connected to ground terminal of a driver IC chip; and cathode connected to control terminal of the switching device; a first resistor connected in parallel with the first diode; a second resistor having a first end connected to the ground of the driver IC chip; a second diode having anode connected to the low side terminal of the switching device and cathode connected to a second end of the second resistor; and a third resistor connected in parallel with the second diode. The Miller clamping circuit is configured to suppress a false turn-on and gate-loop oscillation of the WBG device simultaneously.