Miller Plateau Sampling Circuit for Precise FET Gate Measurement
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Solution Overview
Problem
The short duration of the Miller plateau voltage in power transistors makes it difficult to measure, which is crucial for understanding current conduction through Field Effect Transistors (FETs).
Innovation Solution
A system and method that includes a sampling transistor and capacitor to sample the Miller plateau voltage, using a gate driver to increase the gate voltage to the Miller plateau voltage, and an Analog to Digital Converter (ADC) to measure the voltage, with a diode for decoupling and a sampling capacitance that discharges when the gate voltage decreases, allowing precise measurement of the Miller plateau voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional measurement methods are used to measure Miller plateau voltage, then the measurement can be performed with simple circuitry, but the measurement precision is poor due to the very short duration of the Miller plateau voltage
Solution Approach 1:
The sampling transistor and capacitor are pre-configured to automatically capture the Miller plateau voltage at the precise moment it occurs during FET switching. The circuit is designed to proactively sample the voltage before it disappears, eliminating the need for complex real-time detection and measurement systems.
Solution Approach 2:
A sampling transistor and capacitor are introduced as intermediary components between the Miller plateau voltage source and the measurement system. This intermediary mechanism captures and holds the voltage signal, making it accessible for measurement without requiring complex real-time measurement circuitry.
2Reliability
If the Miller plateau voltage is measured directly without sampling, then the measurement system remains simple, but the measurement cannot be reliably obtained due to the transient nature of the voltage
Solution Approach 1:
The sampling circuit is designed to automatically activate at the precise moment the Miller plateau voltage appears during FET switching. The sampling transistor captures the voltage proactively before it disappears, ensuring reliable measurement without requiring complex real-time detection systems.
Solution Approach 2:
The sampling mechanism operates periodically synchronized with the FET switching cycles, capturing the Miller plateau voltage at each switching event. This periodic sampling ensures that the transient voltage is reliably captured every time it occurs, improving measurement reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable and precise measurement of the Miller plateau voltage, providing valuable information on current conduction through FETs, even under varying environmental conditions, and can trigger safety devices or detect short circuits.
Implementation Method 1
a sampling capacitor connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor
Implementation Method 2
the second gate may be decoupled from the first drain with a diode, wherein the second gate may be connected to an anode of the diode, the first drain may be connected to a cathode of the diode
Data Source
Figure 1
Figure 2
Figure 3~5
AI summary
A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.