MILS Controller I/O Partitioning DMA Isolation
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Solution Overview
Problem
Current Multiple Independent Levels of Security (MILS) systems do not effectively extend partitioning to input/output (I/O) devices, particularly during Direct Memory Access (DMA) operations, where I/O devices can access arbitrary memory regions, compromising security and processor cycles.
Innovation Solution
A system comprising a MILS controller and separation kernel that monitors and controls system transactions, allocates I/O devices to partitions, and tracks memory regions for DMA operations, ensuring isolation and secure access to memory, thereby extending MILS partitioning to I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If I/O devices are allowed to perform DMA operations with high capacity, then data transfer efficiency is improved, but security isolation is compromised because I/O devices can access arbitrary memory regions
Solution Approach 1:
The patent segments the address space into multiple isolated regions, each assigned to specific partitions. The bus controller implements separate address space segments for different security levels, preventing I/O devices from accessing memory regions outside their assigned segment. This segmentation allows DMA operations within each segment while maintaining security isolation between segments.
Solution Approach 2:
The bus controller acts as an intermediary between I/O devices and memory, intercepting and filtering DMA requests. It validates each DMA transaction against the address space segmentation rules, allowing only authorized memory accesses. This intermediary function enables high-capacity DMA operations while enforcing security boundaries that prevent unauthorized access.
2Speed
If I/O devices control the memory bus during DMA operations, then data transfer speed is improved, but processor cycles are consumed when the I/O device controls the bus
Solution Approach 1:
The bus controller is configured to automatically manage DMA transactions without requiring processor intervention. It independently handles address validation, memory access control, and transaction completion for multiple I/O devices. This self-service capability allows the processor to maintain control of the bus for critical operations while I/O devices perform DMA transfers autonomously within their allocated address spaces.
3Reliability
If separate processing environments are used for classified and unclassified information, then security separation is improved, but system complexity increases
Solution Approach 1:
The patent merges multiple security domains into a single processing environment while maintaining logical separation through address space segmentation. The bus controller and MILS controller work together to enforce security boundaries within one system, allowing classified and unclassified information to coexist in the same physical infrastructure. This consolidation reduces the complexity of maintaining separate hardware systems while preserving security isolation through software-controlled address mapping.
Data Source
AI summary
The present invention is a system for providing Multiple Independent Levels of Security (MILS) partitioning. The system includes a memory, a bus controller communicatively coupled to the memory via a memory bus, and a MILS controller communicatively coupled to the bus controller via a host-side bus, the MILS controller configured for monitoring and controlling system transactions. The system further includes a plurality of input/output (I/O) devices communicatively coupled to the MILS controller via a plurality of corresponding device-side buses. The system further includes a MILS separation kernel configured for mapping regions of the memory to a plurality of user partitions. Each I/O device included in the plurality of I/O devices is allocated to a partition included in the plurality of partitions and is isolated from MILS separation kernel space. The MILS separation kernel is configured for guaranteeing isolation of the partitions of the memory. The system further includes a processor connected to the bus controller via a processor front-side bus. The MILS controller is configured for extending MILS partitioning to the plurality of I/O devices.