MIM Capacitor 3D Integration for RF Chip Area Reduction
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Solution Overview
Problem
The metal-insulator-metal (MIM) capacitor area in RF and mixed-signal integrated circuits is limited by chip size parameters, restricting their application in increasingly complex devices.
Innovation Solution
A method of manufacturing packages with MIM capacitors that includes forming MIM capacitors on semiconductor wafers with metallic pillars and polymer layers, followed by a molding compound and interconnect structures to reduce silicon area usage and routing resistance, allowing for efficient integration and connection of chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MIM capacitors are used in RF and mixed-signal integrated circuits, then capacitance density and performance are improved, but chip area is consumed
Solution Approach 1:
The patent implements MIM capacitors as three-dimensional structures formed between intermediate metal levels in the backend-of-line (BEOL) process, transitioning from two-dimensional planar capacitors to vertical 3D structures. This dimensional change allows capacitance to be accumulated in the vertical direction rather than consuming horizontal chip area, thereby improving capacitance density while reducing area consumption.
Solution Approach 2:
The MIM capacitor structure is nested between existing metal interconnect levels in the integrated circuit architecture. The capacitor is formed by depositing metal-insulator-metal layers within the available space between intermediate metal levels, effectively nesting the capacitor structure within the existing BEOL stack without requiring additional external space.
2Adaptability or versatility
If complex RF and mixed-signal applications are implemented, then functionality is improved, but chip size increases
Solution Approach 1:
By implementing MIM capacitors in the vertical dimension between metal levels rather than as large planar structures, the patent enables complex RF and mixed-signal applications to be integrated without proportionally increasing chip area. The vertical stacking allows multiple capacitor elements to be packed into a smaller footprint.
Solution Approach 2:
The MIM capacitor structure provides universal applicability across different RF and mixed-signal circuit designs, serving multiple functions including decoupling, filtering, and oscillating applications. This multi-functional capability allows a single capacitor technology to support increasingly complex applications without requiring different structural approaches for each application type.
3Adaptability or versatility
If MIM capacitors are inserted between intermediate metal levels, then flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The MIM capacitor structure is formed during the backend-of-line (BEOL) manufacturing process by depositing metal-insulator-metal layers on existing intermediate metal levels. This preliminary formation of capacitor structures during the standard manufacturing sequence, rather than as a separate post-processing step, maintains manufacturing flexibility while controlling complexity.
Data Source
AI summary
A package includes a chip that has a metal-insulator-metal (MIM) capacitor formed in a first polymer layer and a metallic pillar formed on the MIM capacitor. A molding compound surrounds the chip, a second polymer layer is formed on the chip and the molding compound, a third polymer layer is formed on the second polymer layer, an interconnect structure is formed between the second polymer layer and the third polymer layer and electrically coupled to the metallic pillar and the MIM capacitor, and a bump is formed over and electrically coupled to the interconnect structure.