Deep Trench MIM Capacitor With Alternating Dielectrics for Low Leakage
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Solution Overview
Problem
Deep trench MIM capacitors in FEOL require additional semiconductor substrate area and suffer from poor signal interference, limiting their effectiveness in achieving large capacitance without increasing chip size.
Innovation Solution
A MIM capacitor design with a capacitor insulator structure comprising alternating dielectric layers, including amorphous tantalum oxide or tantalum-based oxide, and crystalline hafnium oxide layers, is formed in a deep trench to enhance capacitance density and reduce leakage current, utilizing atomic layer deposition (ALD) for precise layer formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a deep trench MIM capacitor is fabricated in the FEOL to achieve large capacitance values, then the capacitance value increases, but the chip area requirement increases and signal interference worsens
Solution Approach 1:
The patent transitions from planar capacitor geometry to a vertical deep trench structure, utilizing the third dimension (depth) to increase capacitance. By forming the capacitor insulator structure with alternating dielectric layers extending vertically into a deep trench, the effective capacitance area is increased without proportionally increasing the lateral chip footprint, thus resolving the contradiction between achieving large capacitance values and minimizing chip area.
2Quantity of substance
If a deep trench MIM capacitor is fabricated in the FEOL to achieve large capacitance values, then the capacitance value increases, but signal interference worsens
Solution Approach 1:
The patent applies local quality by creating alternating layers of amorphous dielectric material and crystalline dielectric material within the capacitor insulator structure. Each layer type provides different local electrical properties - the amorphous layers provide high dielectric constant for capacitance while the crystalline layers provide structural stability and reduced leakage paths. This localized material differentiation reduces signal interference while maintaining high capacitance values.
3Quantity of substance
If alternating amorphous and crystalline dielectric layers are deposited to achieve high capacitance density, then capacitance density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the capacitor insulator structure into alternating layers of amorphous dielectric material and crystalline dielectric material. This segmentation allows each layer type to be optimized independently for its specific function while being deposited using sequential atomic layer deposition processes. The segmented structure achieves high capacitance density through the combined effects of high-k amorphous layers and low-leakage crystalline layers, with the added benefit that each layer can be controlled separately during manufacturing.
Solution Approach 2:
The patent utilizes parameter changes by controlling the deposition conditions and material composition during atomic layer deposition to transition between amorphous and crystalline phases of the dielectric materials. By adjusting deposition temperature, precursor flow rates, and annealing conditions, the manufacturing process can produce the desired alternating amorphous-crystalline layer structure with controlled thickness and material properties, achieving high capacitance density while managing manufacturing complexity through precise parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high capacitance density of over 2000 μF/μm² with reduced leakage current, effectively utilizing a deep trench without increasing chip area, by leveraging the high dielectric constants and amorphous properties of the dielectric layers.
Implementation Method 1
The capacitor insulator structure includes an amorphous layer and crystalline layers. The amorphous layer includes amorphous tantalum oxide or tantalum-based oxide, and the crystalline layers include crystalline hafnium oxide. The design achieves high capacitance density of over 2000 μF/μm² by leveraging the high dielectric constants of these materials.
Implementation Method 2
utilizing atomic layer deposition (ALD) for precise layer formation
Data Source
AI summary
A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.