MIM Capacitor Direct Bond Pad Connection

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Solution Overview

Problem

Conventional metal-insulator-metal (MIM) capacitors built on copper interconnects are costly and have performance limitations due to high resistance and the need for multiple via connections, which are physically constrained and expensive to produce.

Innovation Solution

The MIM capacitor is formed by directly connecting metal bond pads to the copper interconnect layer without via connections, using a dielectric layer between the copper bottom plate and a top plate defined by an extension of the bond pad material, reducing resistance and improving break-down voltage through a modified process involving etching and deposition steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional via connections are used to connect metal plates to interconnect layers, then electrical connection is achieved, but resistance increases and manufacturing cost increases

Engineering Contradiction:
Improveelectrical connection qualityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the via connection structure from the capacitor design, extracting the problematic intermediate connection layer and directly connecting the metal plates to the interconnect layers, thereby eliminating via resistance and simplifying manufacturing

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The metal plates serve dual functions: as capacitor electrodes and as direct electrical connections to interconnect layers, eliminating the need for separate via structures and reducing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple vias are used in parallel to reduce resistance, then resistance decreases, but device complexity increases and manufacturing becomes more difficult

Engineering Contradiction:
ImproveresistanceVSAvoidvia structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent completely removes the via structure from the design, replacing multiple parallel vias with a single direct metal-to-interconnect connection, thereby reducing device complexity while maintaining low resistance

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If conventional MIM capacitor processes are used, then capacitor structure is formed, but manufacturing cost increases due to additional mask layers and process steps

Engineering Contradiction:
Improvecapacitor performanceVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the capacitor formation process with existing interconnect formation steps, combining multiple process steps into a unified flow that reduces the number of mask layers and process steps while maintaining capacitor performance

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The metal plates are formed in advance during interconnect fabrication, and the dielectric layer is subsequently deposited over them, allowing capacitor structures to be created using pre-existing process steps and materials

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11101208B2Metal-insulator-metal (MIM) capacitor
Publication Date: 2021.08.24 MICROCHIP TECHNOLOGY INC
  • US11101208B2 patent drawing
  • US11101208B2 patent drawing
  • US11101208B2 patent drawing

AI summary

A process of forming a metal-insulator-metal (MIM) capacitor may be incorporated into a process of forming metal bond pads connected directly to a top metal interconnect layer (e.g., Cu MTOP). The MIM capacitor may include a dielectric layer formed between a bottom plate defined by the Cu MTOP and a top plate comprising an extension of, or connected directly to, a metal bond pad formed above the Cu MTOP. The process of forming the MIM capacitor may include etching an opening in a passivation layer formed over the Cu MTOP to expose a top surface of the Cu MTOP, forming a dielectric layer extending into the passivation layer opening and onto the exposed Cu MTOP surface, removing portions of the dielectric layer to define a capacitor dielectric, and depositing bond pad metal extending into the passivation layer opening and onto the capacitor dielectric, to define the MIM capacitor top plate.