3D MIM Capacitor Cell Interconnects for Low-Resistance Plates
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Solution Overview
Problem
MIM capacitor architectures face challenges in increasing charge capacitance per unit area while maintaining low electrical resistance, often hindered by higher electrical resistance due to increased plate area.
Innovation Solution
The fabrication of MIM capacitors involves forming cell interconnect structures independently of the cell-level MIM stack, allowing for reduced film thickness and stress constraints, and using conductive materials with optimized thickness and composition to minimize electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM thin film material stack is formed over topographic features of high aspect-ratio to increase charge capacitance per unit area, then charge capacitance per unit area is improved, but plate electrical resistance increases
Solution Approach 1:
The capacitor plate is segmented into multiple conductive regions that are electrically isolated from each other. Each conductive region is formed over a separate high aspect-ratio topographic feature, allowing the plate to be divided into multiple low-resistance segments rather than one large high-resistance plate. This segmentation resolves the contradiction by maintaining high capacitance density while reducing electrical resistance through parallel conduction paths.
Solution Approach 2:
The solution transitions from a two-dimensional plate expansion approach to a three-dimensional structure utilizing vertical topographic features. By forming conductive regions over high aspect-ratio features, the design exploits the vertical dimension to achieve both high capacitance per unit area and low electrical resistance, resolving the contradiction between area efficiency and electrical performance.
2Quantity of substance
If plate area is increased to increase charge capacitance, then charge capacitance is improved, but electrical resistance increases
Solution Approach 1:
The large plate area is segmented into multiple smaller conductive regions, each with lower electrical resistance. These segments are distributed across the capacitor structure, providing multiple parallel conduction paths that collectively achieve the desired capacitance while maintaining low overall resistance, thus resolving the contradiction between capacitance and resistance.
Solution Approach 2:
Different regions of the capacitor plate are given different properties - each local conductive region is optimized for low resistance while the overall distribution of regions achieves high total capacitance. This local optimization approach allows simultaneous achievement of low electrical resistance in each segment and high total charge capacitance across the structure.
Data Source
Figure 1
Figure 2~3B
Figure 4A~4B
AI summary
Capacitor structures that include a cell metal-insulator-metal (MIM) stack within topographic cell containers and cell interconnects that couple the MIM stack of a plurality of cells in electrical parallel to shared capacitor terminals. A first cell interconnect of a first conductive material may span an area under a plurality of the cell containers and a second conductive material of the MIM stack that is confined as a liner of the cell containers is in contact with the first cell interconnect, thereby reducing an electrical resistance of a first shared capacitor electrode. An insulator and another conductive material of the MIM stack is formed within the plurality of cell containers. A second cell interconnect of another conductive material may span an area over a plurality of the cell containers to further couple the MIM stacks of a plurality of cells in electrical parallel to another shared capacitor terminal.