MIM Capacitor Contact Plug Structure for High Capacitance
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Solution Overview
Problem
As semiconductor devices, such as DRAM, integrate denser units, the area of capacitors decreases, leading to increased leakage current when dielectric layer thickness is reduced to enhance capacitance, and high dielectric layers with a lower dielectric layer between the electrode result in undesired capacitance in metal-insulator-semiconductor (MIS) capacitors, necessitating the use of metal-insulator-metal (MIM) capacitors.
Innovation Solution
A semiconductor device design featuring a substrate with multiple electrodes and dielectric layers, including a first electrode with a hole, a first dielectric layer filling the hole, and a second electrode with a second dielectric layer, where a contact plug extends through these layers, isolated from direct contact with the electrodes, and having a stepped sidewall adjacent to the second electrode, increasing contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of capacitor dielectric layers is reduced to increase capacitance, then the capacitance of the capacitors is improved, but the leakage current of the capacitors increases
Solution Approach 1:
The patent employs a composite dielectric structure consisting of a first dielectric layer (higher dielectric constant material) and a second dielectric layer (lower dielectric constant material) stacked in series. This composite structure achieves high capacitance while maintaining low leakage current by combining the advantages of different materials: the first layer provides high capacitance density, while the second layer acts as a barrier to leakage current paths.
2Object-generated harmful factors
If high dielectric layers are used as capacitor dielectric layers, then the leakage current is reduced, but a lower dielectric layer forms between the high dielectric layer and polysilicon upper electrode resulting in undesired capacitance
Solution Approach 1:
The patent extracts and removes the problematic lower dielectric layer that forms between the high dielectric layer and the polysilicon electrode. By eliminating this unwanted layer, the undesired capacitance is removed, allowing the capacitor to achieve the desired capacitance value while maintaining low leakage current characteristics.
3Productivity
If the area of capacitors is reduced to increase integration density, then the productivity is improved, but the capacitance of the capacitors decreases
Solution Approach 1:
The patent changes the dielectric parameters by using materials with higher dielectric constants in the first dielectric layer. This allows the capacitor to achieve high capacitance values in a reduced area, thereby increasing integration density while maintaining the required capacitance. The capacitance is enhanced through material parameter optimization rather than area increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances capacitance while minimizing leakage current by increasing the contact area between electrodes and reducing resistance, effectively addressing the limitations of traditional MIS capacitors.
Implementation Method 1
a first dielectric layer on an upper surface of the first electrode and filling at least a portion of the first hole
Implementation Method 2
a second dielectric layer on the second electrode
Implementation Method 3
a first contact plug extending through the first hole, the second electrode, the second dielectric layer, and the second hole
Data Source
AI summary
A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.