MIM Capacitor Corrugated Profile via Directed Self-Assembly

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Solution Overview

Problem

Integrated circuits (ICs) in deep-submicron process nodes face challenges in providing sufficient power delivery due to limitations in capacitance per unit area, particularly for devices like integrated voltage regulators, where increasing the number of capacitor plates increases manufacturing costs and IC bulk.

Innovation Solution

The implementation of a metal-insulator-metal (MIM) capacitor with a corrugated profile, achieved through directed self-assembly (DSA) techniques or sacrificial layers that segregate into patterns upon heat treatment, allowing for increased capacitance per unit area without the need for additional lithographic operations or increased IC bulk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional planar plate-based MIM capacitors are used, then manufacturing process is simple, but capacitance per unit area is insufficient

Engineering Contradiction:
Improvecapacitance per unit areaVSAvoidcapacitor structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from planar 2D capacitor plates to a 3D corrugated structure with ridges and grooves. This dimensional change increases the effective surface area of the capacitor plates, thereby increasing capacitance per unit area without requiring additional lithographic operations or increasing IC bulk.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces curved/corrugated surfaces instead of flat planar surfaces. The corrugated profile with ridges and grooves increases the surface area of the capacitor plates, enabling higher capacitance per unit area while maintaining compatibility with existing fabrication flows.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Power

If the number of capacitor plates is increased to provide sufficient power delivery, then power delivery capability is improved, but manufacturing cost and IC bulk increase

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidmanufacturing cost
Core Design Contradiction:
PowerVSEase of manufacture

Solution Approach 1:

By transitioning to a 3D corrugated structure, the patent increases the effective capacitance per unit area without adding more capacitor plates or layers. This maintains the same manufacturing process complexity while achieving higher power delivery capability through increased capacitance density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the geometric parameters of the capacitor structure by introducing corrugations with specific ridge and groove dimensions. This parameter change increases the effective surface area and capacitance per unit area, enabling sufficient power delivery without increasing the number of capacitor plates.

Inventive Principle:
Principle #35Parameter changes

3Power

If the number of capacitor plates is increased to provide sufficient power delivery, then power delivery capability is improved, but IC bulk increases

Engineering Contradiction:
Improvepower delivery capabilityVSAvoidIC bulk
Core Design Contradiction:
PowerVSVolume of moving object

Solution Approach 1:

The patent uses vertical corrugations within the existing planar footprint to increase capacitance. This approach increases power delivery capability without expanding the IC area or bulk, as the additional capacitance is achieved through 3D surface structuring rather than adding more plates.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a fourfold or greater increase in capacitance per unit area compared to traditional planar plate-based MIM capacitors, reducing manufacturing costs and enhancing power delivery capabilities while maintaining compatibility with existing fabrication flows.

Implementation Method 1

a sacrificial masking layer of self-organizing material over the first dielectric layer, patterning the masking layer, wherein the patterning includes a non-subtractive process that causes the masking layer to self-organize into distinct structures

Methodology Applied
Scientific EffectPhase separation: Phase Change

Implementation Method 2

a sacrificial layer of material that coalesces into isolated islands when sufficiently heated

Methodology Applied
Scientific EffectHeat treatment: Heat Treatment

Implementation Method 3

depositing a metal-insulator-metal (MIM) capacitor over the patterned first dielectric layer

Methodology Applied
Scientific EffectConformal deposition: Deposition (physical)

Data Source

PatentUS8993404B2Metal-insulator-metal capacitor formation techniques
Publication Date: 2015.03.31 INTEL CORP
  • US8993404B2 patent drawing
  • US8993404B2 patent drawing
  • US8993404B2 patent drawing

AI summary

Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.