Metal-Insulator-Metal Capacitor Integration in Multi-Die Packaging
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Solution Overview
Problem
Existing semiconductor fabrication methods for forming capacitor devices in IC chips are not sufficiently simple or cost-effective, posing challenges as the industry continues to scale down in device size and increase functional density.
Innovation Solution
The integration of a super high-density metal-insulator-metal (SHDMIM) capacitor is achieved through a specific fabrication process involving multiple conductive and dielectric layers, with the capacitor being embedded in a passivation film and utilizing a packaging scheme that includes bonding pads and through-silicon vias for electrical connectivity, allowing for flexible capacitance tuning and increased capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing fabrication processes are used for forming capacitor devices, then the manufacturing process is well-established, but the process complexity and cost are not sufficiently simple or cost-effective
Solution Approach 1:
The patent merges the capacitor formation process with the existing interconnection structure fabrication by using the same metal layers and dielectric materials already present in the IC device. The capacitor electrodes are formed using the existing metal interconnection layers, and the dielectric is formed using the same dielectric material as the interconnection structure, eliminating the need for separate capacitor fabrication processes and reducing overall process complexity
Solution Approach 2:
The patent makes the existing metal layers and dielectric materials serve dual functions: they form both the interconnection structure and the capacitor electrodes and dielectric. This multi-functionality approach allows the same fabrication processes to create both interconnection and capacitor structures, simplifying the manufacturing process and reducing costs
2Productivity
If device scaling continues to increase functional density, then more circuits fit on chip area, but fabrication challenges increase
Solution Approach 1:
The patent combines capacitor fabrication with interconnection structure fabrication into a single integrated process. By forming capacitor electrodes from the same metal layers used for interconnections and using the same dielectric deposition processes, the patent enables increased functional density without proportionally increasing fabrication complexity
Solution Approach 2:
The patent utilizes the vertical dimension by forming capacitors in the z-direction using stacked metal layers and dielectric layers. This three-dimensional approach allows capacitor integration without consuming additional lateral chip area, enabling increased functional density while maintaining fabrication process manageability
3Reliability
If capacitor devices are integrated using conventional methods, then electrical connectivity is achieved, but additional chip real estate is required
Solution Approach 1:
The patent transitions from two-dimensional planar capacitor layouts to three-dimensional vertical capacitor structures by stacking metal layers and dielectric layers in the z-direction. This allows capacitor integration within the existing chip footprint, maintaining electrical connectivity while eliminating the need for additional lateral chip real estate
Solution Approach 2:
The patent nests the capacitor structure within the existing interconnection structure by embedding capacitor electrodes and dielectric between the metal interconnection layers. The capacitor is essentially nested within the same vertical space already allocated for interconnections, achieving dual functionality without expanding the chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces costs, and enhances capacitance values without requiring additional chip real estate, while being compatible with existing processes, thus addressing the limitations of conventional methods.
Implementation Method 1
a first capacitor device comprising a first metal layer, a first dielectric material formed over the first metal layer, a second metal layer formed over the first dielectric material, a second dielectric material formed over the second metal layer, and a third metal layer formed over the second dielectric material
Data Source
AI summary
A device includes a first die and a second die. The first die includes: a first substrate that contains first electrical circuitry, a first interconnection structure disposed over the first substrate, a first dielectric layer disposed over the first interconnection structure, and a plurality of first bonding pads disposed over the first dielectric layer. The second die includes: a second substrate that contains second electrical circuitry, a second interconnection structure disposed over the second substrate, a second dielectric layer disposed over the second interconnection structure, and a plurality of second bonding pads disposed over the second dielectric layer. The first bonding pads of the first die are bonded to the second bonding pads of the second die. At least one of the first die or the second die includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes more than two metal layers that are stacked over one another.