MIM Capacitor Dry Etching Selectivity
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Solution Overview
Problem
Conventional MIM capacitor fabrication processes, particularly the wet etching of top electrode layers, require hard masking layers and result in complex, costly, and less precise capacitor formation, leading to parasitic capacitance and reduced yield due to lateral undercut effects.
Innovation Solution
The implementation of dry etching processes for top electrode layers in MIM capacitors, which eliminates the need for hard masks and achieves high selectivity and precision by using a halogen-based gas mixture in plasma etching, preserving the underlying dielectric layer and improving capacitor matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wet etching is used for top electrode layer, then etching can be achieved, but hard masking layers are required which increases process complexity and cost
Solution Approach 1:
The patent extracts and eliminates the hard masking layer from the etching process by using a selective dry etching chemistry that provides sufficient selectivity between the top electrode and dielectric layer without requiring additional masking materials. This directly resolves the contradiction by removing the source of process complexity while maintaining etching capability.
Solution Approach 2:
The patent replaces the mechanical/chemical masking system (hard mask layers) with a selective chemical etching system that uses plasma chemistry to achieve pattern transfer. The selectivity is achieved through chemical differences between materials rather than physical masking layers, reducing process complexity.
2Ease of manufacture
If wet etching is used for top electrode layer, then etching can be achieved, but lateral undercut effects occur which reduce precision and yield
Solution Approach 1:
The patent replaces wet chemical etching with dry plasma etching, which provides anisotropic (directional) etching characteristics. This substitution eliminates the lateral undercut effect inherent in wet etching while maintaining effective top electrode removal, thereby improving manufacturing precision.
Solution Approach 2:
The patent changes the etching parameters by using plasma-based dry etching with specific gas chemistries (e.g., CHF3, CF4, SF6) that provide both high etch rate and vertical profile control. This parameter change eliminates lateral undercut while maintaining etching effectiveness.
3Quantity of substance
If dielectric layer thickness is decreased to increase capacitance density, then capacitance density increases, but risk of short circuits or leakage between electrodes increases
Solution Approach 1:
The patent changes the dielectric material parameter by using high-k dielectric materials (materials with higher dielectric constants than conventional SiO2). This allows achieving the required capacitance density with thicker dielectric layers compared to conventional materials, thereby maintaining reliability while increasing capacitance density.
Solution Approach 2:
The patent employs composite dielectric structures or high-k dielectric materials that combine high dielectric constant with good breakdown characteristics. This composite approach enables thinner effective dielectric thickness for capacitance while maintaining sufficient breakdown strength to prevent short circuits.
4Quantity of substance
If high-k dielectric materials are used to increase capacitance density, then capacitance density increases, but process complexity may increase
Solution Approach 1:
The patent changes the dielectric material parameter to high-k materials and integrates them into existing CMOS-compatible fabrication processes. By selecting high-k materials that can be deposited using standard PECVD or ALD equipment already present in semiconductor fabs, the patent increases capacitance density while minimizing additions to process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high precision, high density MIM capacitors with improved capacitance density and yield, reducing parasitic capacitance and matching errors, and simplifying the manufacturing process by eliminating the need for hard masks, while maintaining high etch rates suitable for high-volume production.
Implementation Method 1
The implementation of dry etching processes for top electrode layers in MIM capacitors, which eliminates the need for hard masks and achieves high selectivity and precision by using a halogen-based gas mixture in plasma etching
Implementation Method 2
by using a halogen-based gas mixture in plasma etching
Data Source
AI summary
A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.