MIM Capacitor Patterning via Dual Etch Stop Layers
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Solution Overview
Problem
In the formation of semiconductor structures, particularly in 3D ICs, the removal process for MIM capacitors can lead to over-removal of the etch stop layer under the copper bulk, causing corrosion and potential interconnect opens between via plugs and the copper bulk, due to chemical attacks.
Innovation Solution
A method is introduced where a dielectric layer is formed in contact with the etch stop layer, and an additional etch stop layer is formed over it, allowing the MIM capacitor to be patterned without removing the underlying etch stop layer, thus preventing corrosion of the copper bulk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a removal process is used to pattern MIM capacitors, then the MIM capacitor structure can be formed, but the etch stop layer under the copper bulk is over-removed causing corrosion
Solution Approach 1:
An additional etch stop layer is introduced as an intermediary protective layer between the removal process and the original etch stop layer. This additional layer absorbs the chemical attack during MIM capacitor patterning, preventing the removal process from reaching and corroding the copper bulk through the original etch stop layer.
Solution Approach 2:
The additional etch stop layer is formed in advance over the original etch stop layer before the MIM capacitor patterning process. This preliminary protective layer is specifically positioned to prevent chemical attacks during the subsequent removal process, ensuring the copper bulk remains protected.
2Manufacturing precision
If the removal process attacks the etch stop layer, then MIM capacitor patterning is achieved, but interconnect opens occur between via plugs and copper bulk
Solution Approach 1:
The additional etch stop layer serves as a protective intermediary that prevents the removal process chemicals from reaching the copper bulk. This mediator layer allows precise MIM capacitor patterning to occur while maintaining the integrity of the interconnect structure between via plugs and copper bulk.
Solution Approach 2:
The additional etch stop layer acts as a cushioning protective barrier formed beforehand to absorb the chemical attack during the removal process. This prior cushioning prevents direct contact between the chemicals and the copper bulk, ensuring interconnect reliability is maintained throughout the patterning process.
Data Source
AI summary
A method of forming a semiconductor structure includes forming a through-substrate-via (TSV) structure in a substrate. The method includes forming a first etch stop layer over the TSV structure. The method further includes forming a first dielectric layer in contact with the first etch stop layer. The method still further includes forming a second etch stop layer in contact with the first dielectric layer. The method also includes forming a metal-insulator-metal (MIM) capacitor structure in contact with the second etch stop layer. The method further includes forming a first conductive structure through the first etch stop layer and the first dielectric layer, wherein the first conductive structure is electrically coupled with the TSV structure and the TSV structure is substantially wider than the first conductive structure.