MIM Capacitor Layout With Top-Layer Dummy Plates for Etch Tolerance
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Solution Overview
Problem
Existing MIM capacitor structures in semiconductor devices face challenges in maintaining effective area and process tolerance due to the need for dummy plates to address uneven etch loading, which reduces the capacitor's effective area.
Innovation Solution
The method involves implementing top-down enclosure of openings and replacing dummy plates in the bottom conductor plate layer with dummy plates in the top conductor plate layer, along with top-down enclosure of dummy plates, to increase the effective area of the MIM capacitor while maintaining process tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy plates are formed in each conductor plate layer to prevent etch loading, then process tolerance is improved, but the effective area of the MIM capacitor is reduced
Solution Approach 1:
The patent extracts dummy plates from the bottom conductor plate layer and relocates them to the top conductor plate layer. This selective removal and relocation strategy maintains the necessary etch loading balance while preserving the effective area in the bottom layer, thereby resolving the contradiction between process tolerance and effective area.
Solution Approach 2:
The patent shifts the location of dummy plates from the bottom conductor plate layer to the top conductor plate layer, utilizing the vertical dimension (different layers) to redistribute etch loading. This dimensional relocation allows the bottom layer to maintain full effective area while the top layer absorbs the dummy plate area loss.
2Reliability
If openings and dummy plates are formed in conductor plate layers to provide process tolerance, then manufacturing reliability is improved, but the capacitor's effective area is reduced
Solution Approach 1:
The patent extracts dummy plates from the bottom conductor plate layer where they would reduce effective area, and relocates them to the top conductor plate layer. This selective extraction and relocation maintains manufacturing reliability through proper etch loading balance while preserving effective area in the bottom layer.
Solution Approach 2:
The patent utilizes the vertical dimension by moving dummy plates between different conductor plate layers (from bottom to top). This dimensional shift allows the bottom layer to maintain full effective area while the top layer provides the necessary dummy plate coverage for etch loading control, thus maintaining reliability without sacrificing effective area.
Data Source
AI summary
Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.