MIM Capacitor Layout With Square-Wave Edges for Better Frequency Response
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing MIM capacitor designs in integrated circuits face challenges in optimizing the edge layout, leading to poor frequency response due to large areas between the rectangular metal electrode plate edges and metal vias, resulting in increased resistance and reduced capacitance.
Innovation Solution
The proposed solution involves MIM capacitor layouts with metal electrode plates featuring square wave-shaped edges and notched designs, where the straight edges of the top and bottom metal plates are laterally set back from the middle metal plate, reducing the distance between metal vias and edges, thereby minimizing resistance and enhancing frequency response.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If rectangular metal electrode plates are used in MIM capacitor, then the manufacturing process is simple, but the frequency response is poor due to large areas between edges and metal vias
Solution Approach 1:
The metal electrode plates are segmented with notches along their edges, dividing the continuous edge into multiple sections. This segmentation reduces the distance between the plate edges and surrounding metal vias, thereby improving frequency response while maintaining manufacturability through standard photolithography processes
Solution Approach 2:
The metal electrode plates feature asymmetric notched patterns where straight edges are laterally set back from the middle metal plate. This asymmetric design optimizes the distribution of electric fields and reduces parasitic effects, enhancing frequency response without significantly complicating the manufacturing process
2Manufacturing precision
If the distance between metal vias and electrode plate edges is large, then the manufacturing alignment is easier, but the resistance increases and capacitance decreases
Solution Approach 1:
Notches are pre-formed in the metal electrode plates during the patterning process, before subsequent manufacturing steps. This preliminary action ensures that the reduced distance between edges and vias is achieved without compromising alignment tolerance, as the notches are created with controlled dimensions in the lithography step
Data Source
AI summary
An integrated circuit (IC) structure includes a semiconductor substrate, a bottom electrode routing, a capacitor structure, a top electrode routing. The bottom electrode routing is over the semiconductor substrate. The capacitor structure is over the bottom electrode routing. The capacitor structure includes a bottom metal layer, a middle metal layer above the bottom metal layer, and a top metal layer above the middle metal layer. When viewed in a plan view, the top metal layer has opposite straight edges extending along a first direction and opposite square wave-shaped edges connecting the opposite straight edges, the square wave-shaped edges each comprise alternating first and second segments extending along a second direction perpendicular to the first direction, and third segments each connecting adjacent two of the first and second segments, wherein the third segments extend along the first direction.