MIM Capacitor Layout With Edge Protection for Higher Capacitance
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitive elements in integrated circuits occupy a large surface area due to low capacitive value per unit area, and reducing the dielectric layer thickness leads to electrical and chemical degradation, as well as topological constraints.
Innovation Solution
A capacitive element design with a low voltage dielectric layer, covered by a second conductive layer, which includes a central and outer portion electrically connected to avoid tip effects and protect the dielectric layer during manufacturing, allowing for increased capacitive value per unit area without topological constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the thickness of the dielectric layer is reduced to increase capacitive value per unit area, then the capacitive value per unit area increases (double or quadruple), but the dielectric layer undergoes electrical degradation and chemical degradation during manufacturing
Solution Approach 1:
The patent applies local quality by providing enhanced protection (second dielectric layer and protective coating) specifically at vulnerable locations - the edges and corners of the capacitive element where tip effects occur - while maintaining thin dielectric thickness in the central area to maximize capacitance. This localized enhancement resolves the contradiction by protecting critical areas without compromising overall capacitive value.
Solution Approach 2:
The patent implements beforehand cushioning by adding a second dielectric layer and protective coating before manufacturing processes that could cause degradation. These protective structures are prepared in advance to withstand chemical etching and electrical stresses, preventing degradation before it occurs while allowing the primary dielectric layer to remain thin for high capacitance.
2Quantity of substance
If the thickness of the dielectric layer is reduced to increase capacitive value per unit area, then the capacitive value per unit area increases, but tip effects generate electric fields that break down the dielectric layer
Solution Approach 1:
The patent addresses tip effects by applying local quality - adding a second dielectric layer and protective coating specifically at edges and corners where tip effects concentrate electric fields. This localized protection neutralizes harmful electric field concentrations while maintaining thin dielectric thickness in central regions to maximize capacitive value per unit area.
3Reliability
If conventional MIM capacitive elements are manufactured with standard dielectric thickness, then the dielectric layer is protected during manufacturing, but the capacitive value per unit area is low and occupies up to 50% of surface area
Solution Approach 1:
The patent applies parameter changes by reducing the dielectric layer thickness from conventional values to much thinner dimensions (enabling double or quadruple capacitive value per unit area). This parameter change is made possible by simultaneously introducing protective structures (second dielectric layer and protective coating) that compensate for the reduced thickness, thereby maintaining manufacturing robustness while dramatically reducing the surface area required for capacitive elements.
4Ease of manufacture
If wet etching treatments are applied during manufacturing, then other integrated circuit elements are manufactured, but the thin dielectric layer is dissolved with undercut causing reliability problems
Solution Approach 1:
The patent implements beforehand cushioning by introducing a protective coating and second dielectric layer before wet etching treatments. These protective structures act as a barrier during manufacturing processes, preventing the etchant from attacking and dissolving the thin primary dielectric layer, thereby enabling compatibility with standard manufacturing steps while maintaining dielectric layer stability.
Solution Approach 2:
The protective coating and second dielectric layer serve as intermediaries between the thin primary dielectric layer and the harsh wet etching environment. This intermediary protection allows the thin dielectric structure to coexist with aggressive manufacturing processes, enabling ease of manufacture without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design doubles or quadruples the capacitive value per unit area while preventing electrical breakdown and protecting the dielectric layer during manufacturing, maintaining good voltage linearity and compatibility with other integrated circuit elements.
Implementation Method 1
capacitive element comprising: a first conductive layer disposed on a front face of a semiconductor substrate, delimited by an outline, and forming a first electrode of the capacitive element; a low voltage dielectric layer covering the first conductive layer; and a second conductive layer
Implementation Method 2
the breakdown voltage of the dielectric layer 30 is also reduced. Consequently, for operating voltages lower than the breakdown voltage, tip effects TPEF along the ridges and at the vertices of the first conductive layer 10 can generate electric fields which can break down the dielectric layer 30
Data Source
AI summary
A capacitive element includes a first conductive layer delimited by an outline and a low voltage dielectric layer covering the first conductive layer. A second conductive layer covers the low voltage dielectric layer and includes: a first portion located over a central zone of the first conductive layer which forms a first capacitor electrode; and a second portion located over the first conductive layer at the inner border of the entire outline of the first conductive layer, and over the front face at the outer border of the entire outline of the first conductive layer. The first portion and the second portion of the second conductive layer are electrically separated by an annular opening extending through the second conductive layer. The first conductive layer is electrically connected to the second portion of the second conductive layer to form a second capacitor electrode.