MIM Capacitor Spacer Structure for Edge Damage Isolation
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Solution Overview
Problem
MIM capacitors in integrated chips are prone to failure due to moisture and plasma damage at their edges, which are exposed during processing, leading to potential short circuits and reduced reliability.
Innovation Solution
A spacer made of silicon nitride is arranged along the outer sidewalls of the MIM capacitor to protect the lower electrode and capacitor dielectric from moisture and plasma damage, while a capping structure with a smaller footprint for the upper electrode reduces the risk of shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the MIM capacitor edges are exposed during processing, then the manufacturing process is simpler, but the reliability deteriorates due to moisture and plasma damage
Solution Approach 1:
A spacer structure is introduced as an intermediary element between the MIM capacitor edges and the harmful environment. The spacer laterally surrounds the capacitor edges and is in contact with the outer surface of the capacitor dielectric, creating a protective barrier that isolates the capacitor from moisture and plasma damage during processing while maintaining manufacturing simplicity
Solution Approach 2:
The spacer acts as a thin film protective shell that envelops the vulnerable edges of the MIM capacitor. This shell structure provides continuous protection along the capacitor periphery, preventing harmful substances from reaching the capacitor electrodes and dielectric material
2Reliability
If the upper electrode has a larger footprint, then the capacitance increases, but the risk of short circuit increases due to exposure to moisture and plasma
Solution Approach 1:
The spacer serves as a protective intermediary between the upper electrode and the harmful processing environment. By laterally surrounding the upper electrode and contacting the capacitor dielectric outer surface, the spacer creates an isolation barrier that prevents moisture and plasma from causing short circuits, allowing the upper electrode to maintain its functional footprint
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.