MIM Capacitor Electrode Layout for Higher Capacitance in Less Area

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Solution Overview

Problem

The capacitance value and miniaturization of MIM capacitors in semiconductor devices are limited by the smallest interval between wirings in one wiring layer, restricting further enhancement of these components.

Innovation Solution

The design includes a first electrode with a via plug extending along a first direction and a second electrode with a wiring extending orthogonally, allowing for a larger capacitance value by reducing the shortest distance between these components without reducing the facing area, achieved by forming the via plug and wiring in separate steps to minimize alignment errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If both electrodes of MIM capacitor are formed in one wiring layer, then the structure is simple, but the capacitance value is limited by the smallest interval between wirings

Engineering Contradiction:
Improvestructure complexityVSAvoidcapacitance value
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent transitions from a two-dimensional wiring layer configuration to a three-dimensional structure by forming electrodes in different wiring layers. The first electrode is formed in a lower wiring layer and the second electrode in an upper wiring layer, allowing vertical stacking that increases capacitance without being constrained by the minimum interval between wirings in the same layer.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested configuration where the first electrode and second electrode are stacked vertically with the first electrode beneath the second electrode. This nesting approach allows the capacitor to occupy vertical space across multiple wiring layers, effectively increasing the capacitance value while maintaining a compact footprint.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If both electrodes of MIM capacitor are formed in one wiring layer, then the manufacturing process is simple, but the miniaturization is limited by the smallest interval between wirings

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidcapacitor area
Core Design Contradiction:
Ease of manufactureVSVolume of moving object

Solution Approach 1:

The patent utilizes the vertical dimension by forming electrodes in different wiring layers separated by an interlayer insulating film. This vertical stacking approach reduces the horizontal area occupied by the capacitor while maintaining manufacturing feasibility through standard multi-layer wiring processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the capacitor structure into separate segments formed in different wiring layers. The first electrode is formed in one wiring layer and the second electrode in another wiring layer, with each segment manufactured using standard wiring layer processes, thereby maintaining ease of manufacture while achieving miniaturization.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If via plug and wiring are formed in the same step, then the manufacturing process is simple, but alignment errors increase the distance between components

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidalignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the formation process of the via plug and wiring into separate manufacturing steps. The via plug is formed in one step, and the wiring is formed in a subsequent step, allowing each component to be precisely positioned independently. This segmentation enables better alignment control while maintaining overall process simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary formation of the via plug before forming the wiring. This preliminary action allows the via plug to be precisely positioned and established as a reference structure, upon which the wiring can be accurately aligned in a subsequent step, thereby minimizing alignment errors.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20230378050A1Semiconductor device and method of manufacturing the same
Publication Date: 2023.11.23 RENESAS ELECTRONICS CORP
  • US20230378050A1 patent drawing
  • US20230378050A1 patent drawing
  • US20230378050A1 patent drawing

AI summary

A semiconductor device includes a first electrode and a second electrode configuring a MIM capacitor. The first electrode includes a first via plug extending along a first direction. The second electrode includes a second lower wiring extending along the first direction and arranged side by side with the first via plug in a second direction. A length of the first via plug in the first direction is larger than a length of the first via plug in the second direction. A length of the second lower wiring in the first direction is larger than a length of the second lower wiring in the second direction. A length of the first via plug in a third direction is larger than a length of the second lower wiring in the third direction.