MIM Capacitor Electrode Topography for High Capacitance
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Solution Overview
Problem
Conventional capacitors used in semiconductor devices, such as image sensors, face limitations in achieving high capacitance without increasing the dielectric material or doubling up on metal-insulator-metal (MIM) capacitors, which can lead to larger device sizes and complexity.
Innovation Solution
The method involves forming capacitors with electrode topography by depositing metal layers over a substrate, using a diblock copolymer to pattern the metal layers, and depositing dielectric layers to create a metal-insulator-metal (MIM) structure, which increases capacitance by enhancing the surface area without the need for additional capacitors or dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capacitor designs are used, then device size remains compact, but capacitance is insufficient and requires additional capacitors or thicker dielectric layers
Solution Approach 1:
The patent transitions from planar (2D) electrode surfaces to three-dimensional (3D) electrode topography by forming protrusions and recesses on the electrode surfaces. This dimensional change increases the effective surface area of the electrodes, thereby increasing capacitance without requiring additional capacitor units or thicker dielectric layers, thus avoiding increased device complexity.
Solution Approach 2:
The patent applies local quality by creating non-uniform electrode surfaces with specific regions of protrusions and recesses. The electrode topography is locally modified to increase surface area in critical regions, allowing capacitance enhancement without uniformly increasing the entire capacitor structure size or complexity.
2Reliability
If additional capacitors or thicker dielectric layers are used to increase capacitance, then capacitance increases, but device area and complexity increase
Solution Approach 1:
By forming three-dimensional electrode topography with protrusions and recesses, the patent increases the effective surface area of the electrodes within the same planar footprint. This dimensional transformation allows capacitance scaling without increasing the device area, as the additional capacitance comes from the vertical surface area of the topographic features rather than expanding the horizontal device footprint.
Solution Approach 2:
The electrode topography creates a nested structure where protrusions and recesses are formed within the existing electrode layer boundaries. This nesting approach allows the electrode surface to effectively contain more surface area within the same planar dimensions, increasing capacitance without requiring additional device area.
3Reliability
If additional capacitors or thicker dielectric layers are used to increase capacitance, then capacitance increases, but device complexity increases
Solution Approach 1:
The patent achieves capacitance enhancement through three-dimensional electrode topography rather than adding more capacitor units or increasing dielectric thickness. This approach increases capacitance by utilizing the vertical dimension of the electrode surface, avoiding the need for additional capacitor stacks or layers that would increase device complexity.
Solution Approach 2:
The electrode topography is locally engineered with specific protrusion and recess patterns to maximize surface area within the existing capacitor structure. This local modification approach increases capacitance without requiring additional capacitors or complex multi-layer dielectric structures, thereby maintaining simplicity in the overall device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in increased capacitance, potentially doubling it to greater than or equal to 25 femtofarads/square micron, while maintaining a compact design and reducing the need for multiple capacitors, thus simplifying the semiconductor device architecture.
Implementation Method 1
selectively removing a portion of the diblock copolymer, patterning the metal layer using a remaining portion of the diblock copolymer
Implementation Method 2
depositing a first metal layer over a substrate
Implementation Method 3
depositing a dielectric layer over the first metal layer
Data Source
AI summary
Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.