MIM Capacitor Groove Sidewall Electrode Leakage Reduction
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Solution Overview
Problem
MIM capacitors in semiconductor technology are prone to leakage current due to the close proximity of their electrode plates, which affects their stability and frequency characteristics.
Innovation Solution
A method is developed to form MIM capacitors by creating a groove in the dielectric layer to expose the conductive layer, forming a first metal layer on the sidewall and bottom of the groove, and using a sacrificial layer to adjust the position of the first electrode plate, followed by deposition of dielectric and second metal layers, and chemical mechanical polishing to ensure the second electrode plate is level with the dielectric layer, increasing the distance between the electrode plates and reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the electrode plates are placed close together to maintain small capacitor dimensions, then the device size is reduced, but leakage current increases and stability deteriorates
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional structure by forming the first electrode plate on the sidewall of a groove. This vertical arrangement allows the electrode plates to be positioned closer in the vertical dimension while maintaining adequate horizontal spacing, thereby reducing overall capacitor footprint without proportionally increasing leakage current.
Solution Approach 2:
The patent applies different dielectric materials in different regions: a first dielectric material fills the groove where the first electrode plate is formed, while a second dielectric material is used in surrounding regions. This local differentiation allows optimization of electrical properties in the high-field region near the electrode plates while maintaining overall device performance.
2Reliability
If the distance between electrode plates is increased to reduce leakage current, then stability improves, but the capacitor occupies more design space
Solution Approach 1:
By forming the first electrode plate on the groove sidewall rather than as a planar structure, the patent utilizes the vertical dimension to achieve effective electrode separation. The groove depth provides the necessary distance between electrode plates to reduce leakage current while the horizontal footprint remains compact.
Solution Approach 2:
The first electrode plate is nested within the groove structure, with the dielectric material layered around it. This nested arrangement allows the electrode plate to be positioned deep within the capacitor structure, maximizing the distance to the second electrode plate without increasing the overall capacitor width or length.
3Ease of manufacture
If conventional interlayer metal processes are used to form MIM capacitors, then integration with CMOS processes is simplified, but leakage current control becomes difficult
Solution Approach 1:
The patent segments the dielectric structure into distinct regions: a groove region filled with first dielectric material and surrounding regions with second dielectric material. This segmentation allows independent optimization of electrical properties in the critical leakage path region while maintaining compatibility with standard CMOS fabrication processes.
Solution Approach 2:
The groove structure acts as an intermediary element between the two electrode plates, providing a controlled pathway for the electric field. By filling the groove with specific dielectric material, the patent mediates the electrical interaction between electrodes, reducing direct field coupling and leakage current while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current and enhances the stability of MIM capacitors without increasing their design dimensions, maintaining capacitance and improving frequency characteristics.
Implementation Method 1
A dielectric layer 101 is disposed on the substrate 100... The insulating layer 104 is formed on the surface of the first metal layer 103 and serves as a dielectric layer of the MIM capacitor
Implementation Method 2
The third metal layer, the second metal layer, and the dielectric material layer can then be polished using the top surface of the dielectric layer as a stop layer
Data Source
AI summary
Various embodiments provide an MIM capacitor and fabrication method thereof. An exemplary MIM capacitor can include a dielectric layer disposed over a substrate containing a conductive layer. The dielectric layer can include a groove to expose the conductive layer in the substrate. A first metal layer can be disposed on a bottom surface and a bottom portion of a sidewall surface of the groove. A top surface of the first metal layer on the sidewall surface of the groove can be lower than a top surface of the dielectric layer. A dielectric material layer can be disposed on the first metal layer and on a top portion of the sidewall surface of the groove. A second metal layer can be disposed on the dielectric material layer; and a third metal layer can be disposed on the second metal layer to fill the groove.