MIM Capacitor Insulator Segmentation for SoC Voltage and Density
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Solution Overview
Problem
In system-on-chip (SoC) applications, integrating different functional metal-insulator-metal (MIM) capacitors with varying voltage requirements poses a challenge, as thicker insulators for high voltage regions result in smaller capacitance per unit chip-area, while thinner insulators for high-density DRAM capacitors compromise reliability in other regions.
Innovation Solution
A novel integration scheme where MIM capacitors with stacked structures are formed in a common process, using a combination of single and dual dielectric layers to accommodate different voltage requirements, allowing for customized insulator thickness and material in each region to optimize capacitance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thicker insulators are used for high voltage regions, then reliability is improved, but capacitance per unit chip-area decreases
Solution Approach 1:
The patent applies local quality by forming different insulator thicknesses in different regions of the capacitor structure. Specifically, a first insulator layer is formed with a first thickness in a first region, and a second insulator layer is formed with a second thickness in a second region. This allows each region to be optimized for its specific function: thicker insulators in high-voltage regions for reliability, and thinner insulators in DRAM regions for high capacitance density.
Solution Approach 2:
The patent segments the capacitor insulator structure into multiple distinct layers with different thicknesses and materials. The capacitor includes a first insulator layer and a second insulator layer, each with different thicknesses, allowing the structure to be divided into functional regions that can independently optimize for either voltage handling or capacitance density requirements.
2Area of stationary object
If thinner insulators are used for high-density DRAM capacitors, then capacitance per unit chip-area increases, but reliability in other regions deteriorates
Solution Approach 1:
The patent implements local quality by creating region-specific insulator characteristics within a single capacitor structure. The first region contains insulator with first thickness optimized for high capacitance density (DRAM), while the second region contains insulator with second thickness optimized for high voltage reliability. This allows each functional requirement to be satisfied locally without compromising the other.
Solution Approach 2:
The capacitor structure is segmented into multiple insulator layers with different thicknesses. The first insulator layer provides the thin dielectric needed for high-density DRAM capacitors, while the second insulator layer provides the thick dielectric needed for reliable high-voltage operation in other regions, thus segmenting the conflicting requirements into separate structural components.
3Adaptability or versatility
If different capacitor insulator thicknesses are used for different functional circuits, then voltage requirements are met, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication of multiple capacitors with different insulator thicknesses into a single common manufacturing process. By forming both the first and second insulator layers in the same capacitor structure using sequential deposition steps, the process simultaneously produces capacitors optimized for different voltage requirements without requiring separate fabrication lines or complex multi-step processes.
Solution Approach 2:
The capacitor structure is designed with multi-functionality to serve different functional circuits on the same chip. The same basic capacitor architecture can accommodate both high-voltage applications (using the thicker second insulator layer) and high-density DRAM applications (using the thinner first insulator layer), making the structure universal for multiple purposes while simplifying the overall manufacturing approach.
Data Source
AI summary
A system-on-chip (SOC) device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or different thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, a radio frequency region, a dynamic random access memory region, and so forth.