Metal-Insulator-Metal Capacitor Area Reduction via Interconnect Layer Merging
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Solution Overview
Problem
Metal-insulator-metal capacitors in integrated circuits occupy a disproportionate amount of area due to the need for separate contact terminals and routing paths, which can hinder efficient power supply voltage stabilization during mode switching events.
Innovation Solution
The formation of a metal-insulator-metal capacitor within an inter-metal dielectric layer, where the bottom capacitor electrode directly contacts a conductive interconnect line, and the top capacitor electrode overlaps a portion of another interconnect line, with a via connecting them, allowing for reduced area usage by conserving metal layer space and maintaining constant power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate contact terminals and routing paths are formed for metal-insulator-metal capacitors, then the capacitors can be properly connected to circuitry, but the capacitor area occupies a disproportionate amount of space on the integrated circuit
Solution Approach 1:
The patent merges the contact terminal function with existing metal interconnect layers. Instead of forming separate contact terminals, the capacitor electrodes are directly connected to power supply and ground lines that already exist in the metal interconnect layers, eliminating the need for additional terminal structures and reducing overall capacitor area.
Solution Approach 2:
The metal interconnect layers serve multiple functions: they provide both the power supply/ground routing and the capacitor contact terminals simultaneously. This multi-functionality allows the same metal layers to fulfill both routing and terminal connection roles, reducing the area required for dedicated terminal structures.
2Reliability
If metal-insulator-metal capacitors are formed with separate contact terminals, then proper electrical connection is achieved, but the metal layer space is wasted and area efficiency decreases
Solution Approach 1:
The invention combines the terminal formation process with the existing metal interconnect layer structure. The capacitor bottom electrode connects directly to power supply lines and the top electrode connects to ground lines within the same metal layers used for routing, eliminating wasted metal layer space and improving area efficiency.
3Reliability
If decoupling capacitors are formed to provide sufficient capacitance for power supply stabilization, then power supply voltage stability improves, but the capacitor area increases disproportionately
Solution Approach 1:
The patent utilizes the vertical dimension by forming capacitors that extend through multiple metal interconnect layers. The bottom electrode connects to power supply lines in one metal layer while the top electrode connects to ground lines in another metal layer, effectively using the third dimension (vertical stacking) to achieve sufficient capacitance without increasing planar area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces power supply noise and maintains constant voltage levels by acting as a decoupling capacitor without altering the existing circuit layout, thus optimizing area usage and performance.
Implementation Method 1
A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. A capacitor dielectric layer may be subsequently deposited over the first conductive layer.
Implementation Method 2
A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.
Data Source
AI summary
An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.