MIM Capacitor Placement Below Interconnect Metal Layer
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Solution Overview
Problem
The existing manufacturing method for MIM capacitors in BiCMOS ICs faces issues such as over-etching and residue formation due to the roughness of the metal layer, leading to shorts and reduced reliability.
Innovation Solution
The MIM stack is formed below the interconnect metal layer, eliminating the need for formation on top of the nth metal layer, which reduces roughness and allows for a single masking step, thereby avoiding shorts and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the MIM stack is formed on top of the nth metal layer (ME_n), then the capacitor can be connected to the metal layer, but the roughness of the metal layer causes over-etching and residue formation leading to shorts
Solution Approach 1:
The patent inverts the conventional approach by forming the MIM stack below the nth metal layer instead of on top of it. This reversal eliminates the exposure to metal layer roughness during via etching, preventing over-etching and residue formation that cause shorts, while maintaining electrical connection through the metal layer structure
Solution Approach 2:
The patent changes the vertical dimension of MIM stack placement from above the metal layer to below it, integrating the capacitor structure within the interconnect layer stack. This dimensional repositioning allows via etching to proceed without encountering the rough metal surface that causes manufacturing defects
2Ease of manufacture
If the via etching process is used to connect to the bottom plate, then electrical connection is achieved, but the roughness of the metal layer causes the etching to penetrate through the CTM layer creating shorts
Solution Approach 1:
The patent inverts the positioning of the MIM stack relative to the metal layer, placing it below rather than above. This inversion changes the etching path so that vias connect to the bottom plate without penetrating through the CTM layer, eliminating the harmful over-etching effect while maintaining electrical connectivity
3Device complexity
If a single masking step is used to pattern the MIM stack, then manufacturing complexity is reduced, but the metal layer roughness causes residue formation in grooves leading to shorts
Solution Approach 1:
The patent inverts the MIM stack position to below the metal layer, which eliminates the groove formation issues caused by metal roughness. This allows a single masking step to be used effectively without residue formation, reducing manufacturing complexity while maintaining reliability
Solution Approach 2:
The MIM stack is formed in advance below the metal layer before final interconnect processing. This preliminary formation allows subsequent via etching and masking steps to proceed without interference from metal roughness, preventing residue formation that would cause shorts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance, enhances electro-migration properties, and improves MIM reliability by eliminating the need for cold deposition processes and minimizing the risk of early breakdown or leakage.
Implementation Method 1
The MIM stack is formed below the interconnect metal layer
Implementation Method 2
Metal-insulator-metal (MIM) capacitor
Data Source
AI summary
There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilized as an electrical connection to a metal layer of the MIM stack.