MIM Capacitor Integration on Non-Planar Interposer Surfaces
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Solution Overview
Problem
In the semiconductor industry, the integration of decoupling capacitors in three-dimensional ICs faces challenges due to thickness variations and degradation of voltage breakdown, particularly when capacitors are formed on non-planar surfaces with underlying metal features, leading to insufficient routing area in high-density designs.
Innovation Solution
The method involves forming metal-insulator-metal (MIM) capacitors on a substrate interposer, using a series of etch stop layers and insulating layers to create a planar surface, with capacitors positioned between metallization layers and through vias, ensuring a stable and efficient electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If capacitors are formed on non-planar surfaces with underlying metal features, then integration density is improved, but thickness variations and voltage breakdown degradation occur
Solution Approach 1:
The patent applies preliminary planarization by forming an insulating layer over the substrate surface before depositing capacitor structures. This preliminary action creates a flat base surface that prevents thickness variations and voltage breakdown issues when capacitors are subsequently formed, while still allowing high integration density through the underlying non-planar metal features.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the non-planar substrate surface and the capacitor structures. This intermediary layer mediates the conflict by providing electrical isolation and surface planarization, enabling capacitors to be formed on non-planar surfaces without suffering from thickness variations or voltage breakdown degradation.
2Productivity
If capacitors are formed on non-planar surfaces with underlying metal features, then integration density is improved, but voltage breakdown is degraded
Solution Approach 1:
The patent introduces an insulating layer as an intermediary between the non-planar substrate surface and the capacitor structures. This intermediary layer mediates the conflict by providing electrical isolation and surface planarization, enabling capacitors to be formed on non-planar surfaces without suffering from thickness variations or voltage breakdown degradation.
Solution Approach 2:
The patent applies local quality by providing planarization and electrical isolation specifically at the capacitor formation locations through the insulating layer, while maintaining the non-planar metal feature structure in other areas for high integration density. This localized approach preserves reliability without sacrificing productivity.
3Reliability
If capacitors are positioned between metallization layers and through vias, then electrical connection stability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the insulating layer: it provides electrical isolation, surface planarization, and serves as a base for capacitor formation. By combining these functions into a single layer rather than using separate structures, the patent improves electrical connection stability while minimizing the increase in device complexity.
Data Source
AI summary
A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.