MIM Capacitor Using Local Interconnect Metal for High Density
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitors in semiconductor dies require multiple process steps and specialized materials, increasing manufacturing costs and potentially degrading device performance due to their placement between metallization layers over active device layers.
Innovation Solution
A method for fabricating MIM capacitors using a local interconnect metal electrode, where the bottom electrode is formed from gate metal and the top electrode from local interconnect metal, with an interlayer barrier dielectric, allowing for higher capacitance density without additional processing steps, and compatibility with standard CMOS fabrication flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If specialized dielectric and metal layers are used to form MIM capacitors during BEOL processing, then MIM capacitor functionality is achieved, but manufacturing cost increases due to multiple additional process steps and masks
Solution Approach 1:
The patent reuses existing CMOS process layers (gate metal, interlayer barrier dielectric, local interconnect metal) for dual purposes: their primary functions in transistor fabrication and additionally as MIM capacitor electrodes and dielectric. This eliminates the need for specialized MIM capacitor layers, reducing manufacturing cost while maintaining capacitor functionality
Solution Approach 2:
The patent combines MIM capacitor fabrication with standard CMOS transistor fabrication processes by using the same process steps and materials for both structures. The gate metal layer serves as the bottom capacitor electrode, the interlayer barrier dielectric serves as the capacitor dielectric, and the local interconnect metal serves as the top capacitor electrode, merging two fabrication workflows into one
2Quantity of substance
If MIM capacitors are placed between metallization layers over the device layer, then capacitance density is increased, but device performance deteriorates due to adverse effects on CMOS logic device speed
Solution Approach 1:
The patent creates spatially differentiated structures by forming MIM capacitors in specific regions adjacent to transistor gates, using localized gate metal and interlayer barrier dielectric areas. This allows high capacitance density in capacitor regions while leaving transistor active regions unaffected, thereby maintaining device performance while achieving high capacitance where needed
3Reliability
If conventional specialized layers are used for MIM capacitors, then capacitor structure is achieved, but process complexity increases due to additional processing steps beyond standard CMOS flows
Solution Approach 1:
The patent makes existing CMOS process layers serve multiple functions: the gate metal layer becomes both the transistor gate electrode and the bottom MIM capacitor electrode; the interlayer barrier dielectric becomes both the transistor isolation layer and the MIM capacitor dielectric; the local interconnect metal becomes both the transistor interconnect and the top MIM capacitor electrode. This eliminates additional processing steps while achieving complete capacitor structure
Solution Approach 2:
The patent enables existing CMOS layers to serve dual purposes without requiring additional dedicated processes for MIM capacitor fabrication. The standard CMOS fabrication steps automatically create the MIM capacitor structures as a byproduct, making the capacitor fabrication self-service through the existing process flow
Data Source
AI summary
According to one exemplary embodiment, a method for fabricating a metal-insulator-metal (MIM) capacitor in a semiconductor die comprises forming a bottom capacitor electrode over a device layer situated below a first metallization layer of the semiconductor die, and forming a top capacitor electrode over an interlayer barrier dielectric formed over the bottom capacitor electrode. The top capacitor electrode is formed from a local interconnect metal for connecting devices formed in the device layer. In one embodiment, the bottom capacitor electrode is formed from a gate metal. The method may further comprise forming a metal plate in the first metallization layer and over the top capacitor electrode, and connecting the metal plate to the bottom capacitor electrode to provide increased capacitance density.