3D MIM Capacitor Cell Interconnects for Low Plate Resistance
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Solution Overview
Problem
MIM capacitor architectures face challenges in increasing charge capacitance per unit area while maintaining low electrical resistance, often hindered by higher electrical resistance due to increased plate area.
Innovation Solution
The fabrication of MIM capacitors involves forming cell interconnect structures independently of the cell-level MIM stack, allowing for reduced film thickness and stress constraints, and utilizing conductive materials with optimized thickness and composition to minimize electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MIM thin film material stack is formed over topographic features of high aspect-ratio to increase charge capacitance per unit area, then charge capacitance per unit area is improved, but plate electrical resistance increases
Solution Approach 1:
The capacitor plate is segmented into multiple conductive regions (first conductive material in recesses, second conductive material on surface) that are electrically connected through vertical conductive paths. This segmentation allows each region to contribute to capacitance while maintaining low overall resistance through parallel conduction paths.
Solution Approach 2:
The solution transitions from a two-dimensional plate structure to a three-dimensional structure by forming conductive materials within recesses and connecting them vertically. This adds the depth dimension to the capacitor design, enabling increased capacitance density without proportionally increasing resistance.
2Quantity of substance
If plate area is increased to increase charge capacitance, then charge capacitance is improved, but electrical resistance increases
Solution Approach 1:
Different regions of the capacitor structure have different material compositions and thicknesses optimized for their specific functions. The conductive materials in recesses have different properties than those on the surface, allowing local optimization of both capacitance and resistance characteristics.
Solution Approach 2:
The capacitor employs composite conductive structures with multiple materials (first conductive material, second conductive material) having different electrical and mechanical properties. This composite approach enables simultaneous optimization of electrical conductivity and mechanical stress distribution.
3Quantity of substance
If film thickness is reduced to increase capacitance density, then charge capacitance per unit area is improved, but film stress increases
Solution Approach 1:
The invention changes the geometric parameters of the capacitor structure by forming recesses with specific depth-to-width ratios. This parameter optimization allows thin films to achieve high capacitance density while the recess geometry distributes mechanical stress more effectively than flat structures.
Solution Approach 2:
The conductive materials are nested within recesses formed in the dielectric layer, creating a hierarchical structure. This nesting allows the conductive films to be positioned in regions of lower mechanical stress while maintaining electrical functionality.
Data Source
AI summary
Capacitor structures that include a cell metal-insulator-metal (MIM) stack within topographic cell containers and cell interconnects that couple the MIM stack of a plurality of cells in electrical parallel to shared capacitor terminals. A first cell interconnect of a first conductive material may span an area under a plurality of the cell containers and a second conductive material of the MIM stack that is confined as a liner of the cell containers is in contact with the first cell interconnect, thereby reducing an electrical resistance of a first shared capacitor electrode. An insulator and another conductive material of the MIM stack is formed within the plurality of cell containers. A second cell interconnect of another conductive material may span an area over a plurality of the cell containers to further couple the MIM stacks of a plurality of cells in electrical parallel to another shared capacitor terminal.