MIM Capacitor Mask Reduction via Planarized Through Holes
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Solution Overview
Problem
The manufacturing process of Metal-Insulator-Metal (MIM) capacitors requires multiple lithography masks, leading to increased production costs, reduced manufacturing efficiency, and limited capacity due to the complexity and expense of lithography equipment, as well as difficulties in achieving void-free through holes which affect electrical performance.
Innovation Solution
A method for manufacturing MIM capacitors that reduces the number of masks needed by using through holes and conductive-plug through holes in the MIM-capacitor and non-MIM-capacitor regions, respectively, with surface planarization treatment to form recessed structures, allowing for electrical isolation with fewer photolithography steps and improved metal filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple lithography masks are used in the MIM capacitor manufacturing process, then the capacitor can be formed with proper electrical isolation, but the production cost increases and manufacturing efficiency decreases
Solution Approach 1:
The patent combines the formation of through holes and conductive plugs into a single lithography step using one mask, merging two previously separate processes (through hole formation and conductive plug formation) that required multiple masks. This reduces the number of lithography steps while maintaining proper electrical isolation between MIM capacitor regions and non-MIM regions
Solution Approach 2:
The single lithography mask serves multiple functions: it defines both the through holes in the MIM capacitor region and the conductive plugs in the non-MIM region simultaneously. This multi-functional mask replaces multiple specialized masks, reducing cost and process complexity while achieving the same electrical isolation objective
2Reliability
If multiple lithography masks are used in the MIM capacitor manufacturing process, then the capacitor can be formed with proper electrical isolation, but the production cost increases
Solution Approach 1:
The patent combines the formation of through holes and conductive plugs into a single lithography step using one mask, merging two previously separate processes (through hole formation and conductive plug formation) that required multiple masks. This reduces the number of lithography steps while maintaining proper electrical isolation between MIM capacitor regions and non-MIM regions
Solution Approach 2:
The patent eliminates the need for expensive, customized lithography masks by using a single standard mask that can be reused across different production batches. This discards the practice of creating multiple specialized masks for each process step, recovering cost through mask reuse and reduction in mask fabrication expenses
3Reliability
If deep through holes are etched in multiple dielectric layers, then electrical isolation can be achieved, but the etching process becomes more difficult and voids may form
Solution Approach 1:
The patent segments the electrical isolation function into two parts: through holes in the first dielectric layer and conductive plugs in the second dielectric layer. This segmentation allows each structure to be optimized independently - through holes can be etched to appropriate depths without requiring penetration through multiple layers, improving etching quality and reducing void formation
Solution Approach 2:
The conductive plugs act as intermediaries that connect the through holes to upper metal layers. This intermediary structure eliminates the need for deep through holes penetrating multiple dielectric layers, as the conductive plugs provide the necessary electrical connection path, thereby simplifying the etching process and improving manufacturing precision
Data Source
AI summary
Provided are a semiconductor MIM capacitor device and a method for manufacturing the same. The method includes: providing a substrate, and sequentially forming a bottom electrode layer and a first dielectric layer over the substrate; performing patterning on the first dielectric layer by applying a first mask to form a through hole for the MIM-capacitor disposed in the MIM-capacitor region and through holes for the conductive-plugs disposed in the non-MIM-capacitor region; sequentially forming an interconnection metal layer and a second dielectric layer; performing a surface planarization treatment to remove parts of the interconnection metal layer and the second dielectric layer that are outside the through hole of MIM-capacitor and the conductive plugs; and forming an upper metal layer by applying a second mask on surfaces of the second dielectric layer of the through holes of MIM-capacitor and the conductive plugs.