Integrated MIM Capacitor Layout for Mixed-Voltage Semiconductor Chips
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Solution Overview
Problem
The integration of high voltage and low voltage components with a capacitor on a semiconductor device poses challenges due to structural differences, making it difficult to maintain structural integrity and performance during fabrication.
Innovation Solution
A semiconductor device is fabricated with a substrate having distinct regions for high voltage, low voltage components, and a capacitor, where the lower electrode layer of the capacitor is formed within the general gate process, enabling a simplified metal-insulator-metal (MIM) via formation while maintaining structural integrity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage components and low voltage components are integrated on the same chip, then cost is reduced and operating efficiency is improved, but structural differences make it difficult to maintain structural integrity and performance during fabrication
Solution Approach 1:
The patent divides the semiconductor device into distinct high voltage region and low voltage region with separate transistor structures optimized for each voltage regime. The gate dielectric layers, gate electrodes, and capping layers are segmented by region to accommodate different voltage requirements while maintaining overall device integration
Solution Approach 2:
Different gate dielectric layer configurations are applied to different regions: the first transistor in the high voltage region has a first gate dielectric layer with specific properties, while the second transistor in the low voltage region has a second gate dielectric layer with different properties optimized for low voltage operation. This local customization maintains performance while enabling integration
2Ease of manufacture
If the lower electrode layer of the capacitor is formed within the general gate process, then the fabrication process is simplified, but maintaining structural integrity and elemental performance becomes more challenging
Solution Approach 1:
The capacitor fabrication process is merged with the transistor gate formation process. The lower electrode layer of the capacitor is formed simultaneously with the gate electrodes of the transistors using the same deposition and patterning steps, eliminating separate capacitor electrode formation processes and simplifying the overall fabrication flow
Solution Approach 2:
The gate dielectric layers and gate electrodes serve dual functions: they form the active gate structures for the transistors while simultaneously creating the electrode structures for the capacitor. This multi-functionality reduces the total number of process steps while maintaining the required electrical performance of both transistor and capacitor components
Data Source
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AI summary
The present disclosure provides, the semiconductor device includes a substrate, a first transistor, a capacitor, and two first plugs. The substrate has a high-voltage region and a capacitor region. The first transistor is disposed in the high-voltage region, and includes a first gate dielectric layer, a first gate electrode, and a first capping layer. The capacitor is disposed in the capacitor region and includes a second gate electrode, a second capping layer, a dielectric layer, and a conductive layer. The two first plugs are disposed on the capacitor, wherein one of the two first plugs penetrates through the second capping layer to directly contact the second gate electrode, and another one of the two first plugs directly contacts the conductive layer.