MIM Capacitor Trench Layout to Eliminate Barrier Layer Overhang
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Solution Overview
Problem
Complementary metal-oxide semiconductor (CMOS) image sensors face challenges in achieving high capacitance for integrated circuits (ICs) due to the barrier layer overhang issue in deep trench capacitors, which affects capacitance and increases manufacturing costs and resistance, particularly with physical vapor deposition (PVD) and atomic layer deposition (ALD) methods.
Innovation Solution
The barrier layer is formed first and then the capacitor trench is created to expose a portion of the barrier layer, allowing more space for the MIM capacitor, and the barrier layer is formed outside the trench to prevent overhang, using PVD to reduce resistance and enhance IC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the barrier layer is formed before the capacitor trench using conventional methods, then the manufacturing process is simplified, but the barrier layer overhang issue occurs which reduces capacitance and increases resistance
Solution Approach 1:
The barrier layer is formed in advance before the capacitor trench is etched, allowing the barrier material to be deposited conformally on the substrate surface. This preliminary formation enables subsequent trench etching to expose the barrier layer at the trench bottom and sidewalls, eliminating overhang issues while maintaining process simplicity
Solution Approach 2:
The conventional sequence of forming the barrier layer after trench etching is inverted. Instead, the barrier layer is formed first, then the trench is etched through the barrier layer to expose it. This inversion eliminates the overhang problem by allowing the barrier layer to line the trench walls naturally during etching
2Manufacturing precision
If deep trench capacitors are used to increase capacitance, then the capacitance value improves, but the barrier layer overhang issue worsens which increases resistance and reduces performance
Solution Approach 1:
The barrier layer is deposited conformally on the substrate before trench formation, ensuring uniform coverage. When the deep trench is subsequently etched, the barrier layer lines the trench walls without overhanging, allowing for lower resistance while maintaining the high capacitance value achieved through the deep trench structure
Solution Approach 2:
The aspect ratio of the capacitor trench is increased to enhance capacitance while the barrier layer formation timing is changed to prevent overhang. By forming the barrier layer first and then etching the trench to greater depths, the patent achieves higher capacitance without the resistance penalty that would normally accompany deep trench structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the capacitance of MIM capacitors, reduces resistance, and improves the performance of CMOS image sensors by addressing the barrier layer overhang issue and optimizing the manufacturing process.
Implementation Method 1
using PVD to reduce resistance and enhance IC performance
Data Source
AI summary
Provided are an integrated circuit (IC) and a method of forming the same. The IC includes a substrate; a conductive layer, disposed on the substrate; a barrier layer, disposed on the conductive layer; an etching stop layer, covering a sidewall of the barrier layer and extending on a first portion of a top surface of the barrier layer; and at least one capacitor structure, disposed on a second portion of the top surface of the barrier layer.