MIM Capacitor Placement in Package Interconnect Stack
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Solution Overview
Problem
The metal-insulator-metal (MIM) capacitor area in RF and mixed-signal integrated circuits is limited by chip size parameters, hindering the development of increasingly complex applications.
Innovation Solution
A method of manufacturing packages with MIM capacitors involves attaching chips to a carrier wafer, forming MIM capacitors on a second polymer layer, and integrating them with post-passivation interconnect structures to reduce silicon area usage and routing resistance, allowing for flexible placement between metal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MIM capacitors are integrated into RF and mixed-signal integrated circuits, then capacitance density and electrical connection quality are improved, but chip area is consumed
Solution Approach 1:
The patent implements MIM capacitors by utilizing the vertical dimension between intermediate metal levels rather than occupying additional planar chip area. The capacitor structure is formed within the existing three-dimensional metal interconnect stack, transforming a two-dimensional area constraint into a three-dimensional spatial solution that improves electrical connection quality without increasing chip footprint.
Solution Approach 2:
The MIM capacitor structure is nested within the existing metal interconnect architecture. The capacitor is formed by utilizing spaces between intermediate metal levels, effectively nesting the capacitive element within the already-present metal stack structure. This nesting approach allows the capacitor to share the same physical space that would otherwise be used for routing, thereby improving reliability without consuming additional chip area.
2Ease of manufacture
If chip size is reduced to lower costs, then manufacturing cost is reduced, but MIM capacitor area is limited
Solution Approach 1:
By forming MIM capacitors in the vertical space between intermediate metal levels, the patent enables capacitor integration within smaller chip footprints. This dimensional approach allows reduced chip size for cost reduction while maintaining adequate capacitor area, as the capacitor utilizes the vertical dimension rather than requiring additional planar space.
Solution Approach 2:
The patent changes the spatial parameters of capacitor placement from horizontal expansion to vertical utilization. By adjusting the configuration to use the third dimension (vertical space between metal levels), the system achieves adequate capacitance values even when chip area is reduced, thereby enabling cost-effective manufacturing without sacrificing capacitor performance.
3Adaptability or versatility
If more complex RF and mixed-signal applications are implemented, then functionality is improved, but routing resistance increases
Solution Approach 1:
The MIM capacitor serves as an intermediary element that provides decoupling and filtering functions, improving the functionality of complex RF and mixed-signal applications. By placing the capacitor close to the circuit nodes that require decoupling, the patent reduces the routing distance and associated resistance, thereby enabling more complex functionality with minimized energy loss in the interconnect paths.
Data Source
AI summary
A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.