MIM Capacitor Shielding for Parasitic Capacitance Reduction
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Solution Overview
Problem
In display devices, the parasitic capacitance between the output capacitor and other metal layers leads to deviations in capacitance, causing inaccuracies in charge redistribution and output voltage, particularly due to the use of single-layer capacitors which are not effectively shielded.
Innovation Solution
The circuit device employs a configuration with a first and second MIM capacitor element, where the first metal layer and fourth metal layer are coupled to the capacitor drive node, and the second metal layer and third metal layer are coupled to the voltage output node, with the second and third metal layers positioned to be shielded by the first and fourth metal layers, reducing parasitic capacitance and ensuring accurate charge redistribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer capacitor is used to implement the output capacitor in an integrated circuit, then the device complexity is reduced and ease of manufacture is improved, but parasitic capacitance is formed between the upper layer of the capacitor and other metal layers, leading to deviation in capacitance and output voltage
Solution Approach 1:
The patent embeds shield electrodes (third and fourth metal layers) within the capacitor structure itself, nesting them between the capacitor electrodes. This internal shielding approach eliminates the need for separate external shielding structures while reducing parasitic capacitance between the capacitor and surrounding metal layers, thereby improving capacitance precision without significantly increasing manufacturing complexity
Solution Approach 2:
The patent introduces shield electrodes as intermediary elements between the output capacitor and other metal layers. These shield electrodes act as mediators that block parasitic capacitance coupling, preventing the harmful electrical interaction between the capacitor and surrounding circuitry, thus improving capacitance precision while maintaining a relatively simple manufactured structure
2Area of stationary object
If the upper layer of the single-layer capacitor is used as an output node, then the layout area is reduced, but parasitic capacitance occurs between the upper layer and wiring layers disposed above, causing deviation in output voltage
Solution Approach 1:
The patent nests shield electrodes (third and fourth metal layers) directly within the capacitor structure, with the third metal layer positioned between the second metal layer and surrounding wiring layers. This internal nesting provides electromagnetic shielding that prevents parasitic capacitance coupling, ensuring output voltage accuracy while maintaining a compact layout area
Solution Approach 2:
The patent applies preliminary anti-action by pre-positioning shield electrodes before the harmful parasitic capacitance can form. The third and fourth metal layers are configured in advance to counteract the parasitic capacitance effect between the capacitor and overhead wiring layers, preventing voltage accuracy degradation before it occurs
3Productivity
If charge redistribution is used to output voltage rapidly, then the productivity is improved, but parasitic capacitance causes deviation in capacitance distribution ratio, leading to inaccurate output voltage
Solution Approach 1:
The patent introduces shield electrodes as intermediary elements that mediate between the charge redistribution process and parasitic capacitance effects. These shield electrodes block the parasitic capacitance coupling during charge redistribution, ensuring that the capacitance distribution ratio remains accurate while maintaining high-speed voltage output capability
Solution Approach 2:
The patent converts the potentially harmful parasitic capacitance effect into a beneficial shielding configuration. By strategically positioning the third and fourth metal layers, the structure that could have caused parasitic capacitance is transformed into an active shielding mechanism that reduces parasitic capacitance, thereby improving output voltage precision during rapid charge redistribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for accurate charge redistribution and output voltage, reduces the layout area of the output capacitor, and minimizes parasitic capacitance, resulting in improved performance and efficiency in display devices.
Implementation Method 1
parasitic capacitance may be formed between the upper layer of the single-layer capacitor and another metal layer or the like
Data Source
AI summary
A circuit device includes a driving circuit and an output capacitor. The output capacitor includes a first MIM capacitor element including a first metal layer, a second metal layer, and a first insulating layer, and a second MIM capacitor element including a third metal layer, a fourth metal layer, and a second insulating layer. The first metal layer and the fourth metal layer are electrically coupled to the capacitor drive node, and the second metal layer and the third metal layer are electrically coupled to the voltage output node. The second metal layer is positioned at the third metal layer side with respect to the first metal layer, and the third metal layer is positioned at the second metal layer side with respect to the fourth metal layer.