MIM Capacitor Passivation Structure for Recess and Breakdown Control

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Solution Overview

Problem

Existing processes for manufacturing metal-insulator-metal (MIM) capacitors in semiconductor integrated circuits face challenges as device scaling-down continues, particularly in maintaining satisfactory performance and preventing dielectric breakdown voltage failure and recess loading in iso-dense areas.

Innovation Solution

Incorporating a buffer layer with a thickness of about 50% to 100% of the barrier layer's thickness to protect the passivation layer during the removal of the barrier layer, and using an adhesion layer with tensile stress and a passivation layer with compressive stress to enhance adhesion and reduce stress-related failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device scaling-down continues to increase functional density, then the number of interconnected devices per chip area increases, but dielectric breakdown voltage failure and recess loading in iso-dense areas worsen

Engineering Contradiction:
Improvefunctional densityVSAvoiddielectric breakdown voltage failure
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the passivation layer into multiple thickness regions: a first thickness in non-iso-dense areas and a greater second thickness in iso-dense areas. This segmentation allows the structure to provide enhanced protection specifically where needed (iso-dense areas) while maintaining overall functional density, thereby preventing dielectric breakdown voltage failure without compromising productivity.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If barrier layer is removed completely to access underlying structures, then manufacturing access is improved, but passivation layer becomes vulnerable to recess loading and damage

Engineering Contradiction:
Improvemanufacturing accessVSAvoidpassivation layer integrity
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The patent applies beforehand cushioning by forming a buffer layer between the barrier layer and the passivation layer. When the barrier layer is removed during manufacturing, the buffer layer remains to cushion and protect the passivation layer from recess loading and damage, thereby maintaining passivation layer integrity while still allowing manufacturing access.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Strength

If adhesion layer with tensile stress is used to enhance bonding, then adhesion strength improves, but stress-related failures may occur in the redistribution layer

Engineering Contradiction:
Improveadhesion strengthVSAvoidstress-related failures
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

The patent applies the anti-weight principle by using an adhesion layer with tensile stress to counterbalance the compressive stress in the passivation layer. This stress compensation mechanism prevents stress-related failures in the redistribution layer while maintaining strong adhesion, as the tensile stress in the adhesion layer offsets the compressive stress that would otherwise cause delamination or cracking.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces dielectric breakdown voltage failure and improves recess loading in iso-dense areas by preventing passivation layer recessing and ensuring robust adhesion and stress protection for the redistribution layer.

Implementation Method 1

an adhesion layer with tensile stress and a passivation layer with compressive stress to enhance adhesion and reduce stress-related failures

Methodology Applied
Scientific EffectStress:

Data Source

PatentUS20240371920A1Device structure and methods of forming the same
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371920A1 patent drawing
  • US20240371920A1 patent drawing
  • US20240371920A1 patent drawing

AI summary

A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.