MIM Capacitor Upper Electrode Layout for Smaller Chip Periphery
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Solution Overview
Problem
In semiconductor manufacturing, the formation of metal-insulator-metal (MIM) capacitors results in upper electrodes extending into the periphery region, leading to increased chip size due to the need for spacing contacts from the extended electrodes to prevent short circuits.
Innovation Solution
A method where a protective layer and doped layer are used to mask and selectively etch the upper electrode in the periphery region, ensuring it does not extend into the periphery, allowing contacts to be positioned closer to the capacitor without contact, thereby minimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the photoresist layer covers the metal layer in both capacitor region and periphery region to prevent short circuits, then the reliability is improved, but the area of periphery region increases leading to increased chip size
Solution Approach 1:
The patent divides the chip into capacitor region and periphery region, and further segments the metal layer into first metal layer (in capacitor region) and second metal layer (in periphery region). By applying different photoresist patterns to different regions, the upper electrode is confined to the capacitor region only, allowing contacts in the periphery region to be positioned closer without causing short circuits, thus reducing overall chip size while maintaining reliability
Solution Approach 2:
The patent applies different photoresist coverage strategies to different regions: in the capacitor region, the photoresist covers the metal layer to form the upper electrode, while in the periphery region, the photoresist does not cover the metal layer, preventing the upper electrode from extending into the periphery region. This localized differentiation allows contacts to be placed closer to the capacitor region without risk of short circuits, reducing chip size while maintaining reliability
2Manufacturing precision
If the upper electrode extends into the periphery region to ensure complete overlap with insulating layer and lower electrode, then the manufacturing precision is improved, but the area of periphery region increases leading to increased chip size
Solution Approach 1:
The patent segments the metal layer into first metal layer (in capacitor region) and second metal layer (in periphery region), and segments the photoresist coverage accordingly. The upper electrode is formed only over the first metal layer in the capacitor region, ensuring complete overlap with the insulating layer and lower electrode where needed, while preventing extension into the periphery region. This segmentation allows precise control of electrode placement without increasing chip size
Solution Approach 2:
The patent implements different photoresist coverage characteristics in different regions: full coverage in the capacitor region to ensure complete overlap and manufacturing precision, and no coverage in the periphery region to prevent electrode extension. This local quality approach ensures the upper electrode achieves complete overlap with insulating layer and lower electrode in the capacitor region while maintaining compact chip dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a reduction in chip size by ensuring the upper electrode does not encroach into the periphery region, enabling contacts to be placed closer to the capacitor without short circuits, thus optimizing semiconductor structure layout.
Implementation Method 1
An etching process is performed using the doped layer as a mask to remove the protective layer and the upper electrode layer in the periphery region
Data Source
AI summary
Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.