Semiconductor device manufacturing method
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Solution Overview
Problem
The existing process of forming a MIM capacitor and a thin film resistor in semiconductor devices requires separate patterning and additional photo lithography and etching processes, leading to increased time and cost.
Innovation Solution
A method is introduced where a first and second barrier metal layer is deposited, followed by a dielectric layer, and then simultaneously etched to form both the MIM capacitor and thin film resistor regions, with a two-stage etching process using chlorine-based and nitrogen-based or oxygen-based plasma, and a cleaning operation with TMAH solution to remove residues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate patterning processes are used for MIM capacitor and thin film resistor, then pattern formation precision is maintained, but manufacturing complexity and process time increase
Solution Approach 1:
The patent combines the patterning processes for MIM capacitor and thin film resistor into a single unified process. A common mandrel structure is formed first, then a single etching process simultaneously defines both the capacitor electrodes and resistor regions. This merging eliminates the need for separate photolithography and etching steps that would otherwise be required for each component, thereby reducing manufacturing complexity while maintaining pattern precision through the unified process design.
Solution Approach 2:
The mandrel structure serves multiple functions: it acts as a pattern definition template for both the MIM capacitor electrodes and the thin film resistor regions. The same mandrel and etching process that defines the capacitor geometry also simultaneously defines the resistor geometry, making the patterning system universal for both component types rather than requiring separate specialized processes for each.
2Manufacturing precision
If additional photo lithography and etching processes are added, then pattern definition accuracy is improved, but productivity decreases
Solution Approach 1:
The patent merges multiple sequential processes (photolithography for capacitor, photolithography for resistor, etching for capacitor, etching for resistor) into a single integrated process sequence. One photolithography step deposits a common resist pattern, and one etching step simultaneously creates both capacitor and resistor features. This consolidation maintains pattern definition accuracy through proper process sequencing while doubling productivity by eliminating redundant process cycles.
Solution Approach 2:
The patent performs preliminary actions by forming a common mandrel structure and applying a single resist pattern before the final etching step. This preliminary patterning establishes the geometric framework for both components simultaneously, allowing the subsequent etching process to efficiently create both capacitor and resistor features in one operation rather than requiring separate preliminary and final steps for each component.
3Reliability
If separate processes are used for MIM capacitor and thin film resistor formation, then component quality is maintained, but manufacturing cost increases
Solution Approach 1:
The patent combines the formation processes for MIM capacitors and thin film resistors into a single integrated manufacturing flow. By using common materials layers (such as TiN and TaN deposited in the same sequence), unified patterning steps, and simultaneous etching processes, the manufacturing cost is reduced through economies of scale and process consolidation while maintaining component quality through controlled process parameters and material selection.
Solution Approach 2:
The patent employs universal materials and processes that serve both capacitor and resistor fabrication. The same barrier metal layers, dielectric layers, and etching chemistries are used for both component types, eliminating the need for separate specialized process lines. This universality reduces manufacturing cost by simplifying the overall process architecture while maintaining component quality through consistent material properties and process control across both device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of photolithography and etching processes, saving time and cost while maintaining the integrity of the devices, thereby improving productivity and economic efficiency.
Implementation Method 1
performing a first etching of the second barrier metal layer with a chlorine-based plasma
Implementation Method 2
performing a second etching of the first dielectric layer with one of a nitrogen-based plasma and an oxygen-based plasma
Implementation Method 3
performing a cleaning operation with a Tetra Methyl Ammonium Hydroxide (TMAH) solution, and removing a by-product of the second barrier metal layer
Implementation Method 4
depositing a first barrier metal layer on the first interconnect metal layer; depositing Ti and TIN on the first interconnect metal layer; depositing a second barrier metal layer on the first dielectric layer; depositing TaN on the first dielectric layer
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes depositing a first interconnect metal layer on a substrate; depositing a first barrier metal layer on the first interconnect metal layer; depositing a first dielectric layer on the first barrier metal layer; depositing a second barrier metal layer on the first dielectric layer; etching the second barrier metal layer to form a MIM capacitor region and a thin film resistor region; forming a hard mask on the second barrier metal layer and the first dielectric layer; forming an isolated interconnect pattern between the MIM capacitor region and the thin film resistor region; depositing an inter-metal dielectric layer on the hard mask; forming Via holes in the MIM capacitor region and the thin film resistor region, and filling the Via holes with metal to form a Via contact layer.