Three-Plate MIM Capacitor Layout for Scaled IC Area Limits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Typical metal-insulator-metal (MIM) devices fail to provide sufficient capacitance per unit area as integrated circuits (ICs) are scaled down, making them unsuitable for applications requiring increased performance.

Innovation Solution

A MIM device with three metal plates and two capacitor insulator structures, where each metal plate is electrically coupled to a conductive contact, allowing for increased capacitance by summing the capacitance between each plate pair, thereby enhancing performance for a given layout area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a typical MIM device with two metal plates is used, then the device structure is simple, but the capacitance per unit area is insufficient for scaled-down ICs

Engineering Contradiction:
Improvecapacitance per unit areaVSAvoiddevice structure
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements a nested capacitor structure where a third metal plate is positioned between the first and second metal plates, creating nested capacitive regions. The first capacitor is formed between the first metal plate and the third metal plate, while the second capacitor is formed between the third metal plate and the second metal plate. This nesting arrangement effectively doubles the capacitance per unit area compared to a conventional two-plate MIM device, resolving the contradiction between maintaining structural simplicity and achieving higher capacitance density.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent transitions from a planar two-plate configuration to a three-dimensional stacked configuration with three metal plates separated by insulator layers. By adding the vertical dimension and inserting a third metal plate between the original two plates, the device achieves increased capacitance per unit area without significantly increasing the lateral footprint, thus resolving the contradiction between capacitance density and device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If ICs are scaled down to small single or dual pixel sizes, then the device footprint is reduced, but the capacitance per unit area becomes insufficient

Engineering Contradiction:
Improvecapacitance per unit areaVSAvoidlayout area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The nested three-plate configuration allows the capacitor to achieve doubled capacitance per unit area within the same lateral footprint. This is critical for scaled-down ICs with small single or dual pixel sizes, as it provides the required capacitance without increasing the layout area, effectively resolving the contradiction between capacitance density and available area.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

By utilizing the vertical dimension with stacked metal plates and insulator layers, the patent achieves higher capacitance per unit area without expanding the lateral layout area. This dimensional transition enables the device to meet capacitance requirements in scaled-down IC architectures where lateral space is constrained.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The MIM device achieves improved capacitance for a given layout area, enabling its use in applications that typical MIM devices cannot support, such as ICs with small single or dual pixel sizes.

Implementation Method 1

A first capacitor insulator structure is disposed between the first metal plate and the second metal plate and electrically insulates the first metal plate from the second metal plate

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

The MIM device comprises a first metal plate, a second metal plate over the first metal plate, and a third metal plate over the second metal plate. A first capacitor insulator structure is disposed between the first metal plate and the second metal plate

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS11854959B2Metal-insulator-metal device with improved performance
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11854959B2 patent drawing
  • US11854959B2 patent drawing
  • US11854959B2 patent drawing

AI summary

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.