MIM Capacitor Serrate Sidewalls via Selective Wet Etch
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Solution Overview
Problem
Conventional methods for increasing the capacitance of metal-insulator-metal (MIM) capacitors in DRAM devices result in high aspect ratios for bit line contact holes, complicating the process and increasing costs due to the need for thick insulator layers and complex etching processes.
Innovation Solution
A method involving the alternation of second and third dielectric layers with a high wet etch selectivity is used to form serrate sidewalls and lateral recesses, allowing for increased capacitance without altering the bit line contact aspect ratio, by depositing a stack dielectric structure and performing a wet etch process to create a serrate profile, followed by the formation of bottom and top electrode layers with a high-k dielectric layer in between.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a thick insulator layer is formed in openings to increase the vertical dimension of the crown-shaped capacitor structure, then the capacitance is increased, but the aspect ratio of bit line contact holes becomes high
Solution Approach 1:
The patent transitions from a conventional single-layer capacitor structure to a multi-layer stack dielectric structure with alternating high-k and low-k dielectric layers. This vertical stacking approach increases capacitance by utilizing multiple interfaces and higher dielectric constants, while maintaining a more manageable aspect ratio compared to forming a single thick insulator layer.
Solution Approach 2:
The patent employs a composite dielectric structure consisting of alternating high-k dielectric layers (such as BaTiO3, Pb(Zr,Ti)O3, or Pb1-xLaxZr1-yTiyO3) and low-k dielectric layers. This composite structure leverages the high capacitance contribution from high-k layers while using low-k layers to reduce parasitic effects and improve overall capacitor performance, achieving higher capacitance without proportionally increasing the aspect ratio.
2Quantity of substance
If a thick insulator layer is formed to increase capacitance, then the capacitance is increased, but the process complexity and cost increase
Solution Approach 1:
The patent divides the capacitor structure into multiple discrete layers with alternating high-k and low-k dielectric materials. Each layer can be deposited and processed separately using standard semiconductor fabrication techniques, allowing for modular manufacturing. This segmentation enables better process control and yields compared to forming a single thick insulator layer, reducing overall process complexity.
Solution Approach 2:
The patent utilizes parameter changes in dielectric constant (k-value) across different layers to achieve higher capacitance. By alternating between high-k and low-k dielectric materials with different permittivity values, the structure optimizes capacitance while maintaining manufacturability through controlled deposition parameters and standard fabrication processes.
3Quantity of substance
If a thick insulator layer is formed to increase capacitance, then the capacitance is increased, but the anisotropic etching of bit line contact holes becomes difficult
Solution Approach 1:
The patent addresses the anisotropic etching difficulty by changing the vertical dimensioning approach. Instead of relying on a single thick insulator layer that requires deep, narrow contact holes with high aspect ratios, the multi-layer stack structure distributes the capacitance function across multiple thinner layers. This reduces the required depth of individual contact holes, making anisotropic etching more controllable and manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the total effective capacitance of MIM capacitors while maintaining the aspect ratio of bit line contact holes, simplifying the process and reducing costs by using a controlled wet etch process with high selectivity between dielectric layers.
Implementation Method 1
By performing a wet etch process, relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers are removed to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening
Implementation Method 2
A wet etch selectivity of the second dielectric layer relative to the third dielectric layer is of at least 5:1
Data Source
AI summary
A method of forming a metal-insulator-metal capacitor has the following steps. A stack dielectric structure is formed by alternately depositing a plurality of second dielectric layers and a plurality of third dielectric layers. A wet etch selectivity of the second dielectric layer relative to said third dielectric layer is of at least 5:1. An opening is formed in the stack dielectric structure, and then a wet etch process is employed to remove relatively-large portions of the second dielectric layers and relatively-small portions of the third dielectric layers to form a plurality of lateral recesses in the second dielectric layers along sidewalls of the opening. A bottom electrode layer is formed to extend along the serrate sidewalls, a capacitor dielectric layer is formed on the bottom electrode layer, and a top electrode layer is formed on the capacitor dielectric layer.