MIM Capacitor Sidewall Layout for Stable Breakdown Voltage
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Solution Overview
Problem
Current metal-insulator-metal (MIM) capacitors face challenges in achieving optimal frequency response and breakdown voltage stability due to parasitic resistance and leakage current issues, particularly in corner regions where vertical sidewalls lead to dielectric breakdown voltage tailing.
Innovation Solution
The implementation of a semiconductor device with MIM capacitors featuring tapered sidewalls on the bottom and middle electrodes, along with a vertical sidewall on the top electrode, reduces leakage current and enhances dielectric breakdown voltage stability by allowing a thicker insulating dielectric layer to land more densely in corner regions, thereby mitigating breakdown voltage tailing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vertical sidewalls are used in MIM capacitor electrodes, then fabrication is simpler, but leakage current increases and breakdown voltage stability deteriorates due to dielectric breakdown voltage tailing in corner regions
Solution Approach 1:
The patent applies asymmetry by transitioning from symmetric vertical sidewalls to asymmetric tapered sidewalls with different angles on opposite sides of the electrode structures. This asymmetric geometry allows the insulating dielectric layer to land more densely in corner regions, reducing leakage current and eliminating breakdown voltage tailing while maintaining fabrication feasibility through modified etching processes
2Device complexity
If vertical sidewalls are used in MIM capacitor electrodes, then device structure is simpler, but parasitic resistance increases and frequency response deteriorates
Solution Approach 1:
The asymmetric tapered sidewall design modifies the electrode geometry to reduce parasitic resistance in corner regions. By creating non-uniform sidewall angles, the structure optimizes current distribution and reduces contact resistance, thereby improving frequency response without significantly increasing overall device complexity
Solution Approach 2:
The patent applies local quality by implementing different sidewall angles in different regions of the electrode structure. The tapered sidewalls with varying angles (e.g., 45-60 degrees on one side, 30-45 degrees on the other) locally optimize the corner regions where parasitic resistance is most problematic, while maintaining simpler geometry in other areas
3Reliability
If thicker insulating dielectric layer is deposited, then breakdown voltage stability improves, but leakage current increases in corner regions with vertical sidewalls
Solution Approach 1:
The asymmetric tapered sidewall configuration resolves the contradiction between thicker dielectric layers and leakage current by creating non-uniform landing angles. This asymmetry allows the dielectric layer to achieve optimal thickness and density distribution, maintaining high breakdown voltage stability while preventing excessive leakage current in corner regions through improved material deposition geometry
Data Source
AI summary
The present disclosure is directed to a semiconductor device. The semiconductor device includes a substrate, an insulating layer disposed on the substrate, a first conductive feature disposed in the insulating layer, and a capacitor structure disposed on the insulating layer. The capacitor structure includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, and a third electrode sequentially stacked. The semiconductor device also includes a first via connected to the first electrode and the third electrode, a second via connected to the second electrode, and a third via connected to the first conductive feature. A part of the first via is disposed in the insulating layer. A portion of the first conductive feature is directly under the capacitor structure.