MIM Capacitor Stack Patterning With a Single Mask

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Solution Overview

Problem

The existing methods for manufacturing metal-insulator-metal (MIM) capacitors in integrated chips require multiple masks and complex photolithography processes, which increase fabrication costs and complexity, and may lead to higher contact resistance due to the number of layers involved.

Innovation Solution

A method is developed to form MIM capacitors using a minimum mask approach, where a single mask layer is used to pattern a stack structure of conductive and insulating layers, reducing the number of photomasks and processes, and achieving a stepped structure with electrodes and insulating layers alternately stacked, allowing for lower contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple masks and complex photolithography processes are used to manufacture MIM capacitors, then the capacitor structure can be formed with multiple layers, but the fabrication cost and process complexity increase

Engineering Contradiction:
Improvecapacitor structure formationVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple photolithography steps into a single patterning process. Specifically, it forms a stack structure with alternating conductive and insulating layers, then uses one mask to pattern all layers simultaneously through selective etching, eliminating the need for multiple separate photolithography steps that would otherwise be required to form each layer individually.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the capacitor formation process into distinct etching steps that selectively remove materials from the stack structure. By segmenting the etching process into multiple selective steps (first etching conductive layers, then insulating layers, then remaining conductive layers), it achieves complex 3D capacitor structures from a single stacked precursor structure.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If multiple masks and photolithography processes are used, then the capacitor layers can be precisely patterned, but the fabrication cost increases

Engineering Contradiction:
Improvelayer patterning precisionVSAvoidfabrication cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent combines multiple patterning operations into a single mask step. The stack structure approach allows one photomask to define the pattern for all conductive and insulating layers simultaneously, reducing material costs (fewer masks) and process costs (fewer photolithography cycles) while maintaining precise patterning through selective etching processes.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11862665B2Semiconductor structure including MIM capacitor and method of forming the same
Publication Date: 2024.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11862665B2 patent drawing
  • US11862665B2 patent drawing
  • US11862665B2 patent drawing

AI summary

A method of forming a semiconductor structure including a metal-insulator-metal (MIM) capacitor includes: forming a stack structure over a substrate, wherein the stack structure includes a plurality of electrode material layers and a plurality of insulating material layers alternately stacked over the substrate; forming a mask layer on the stack structure; and performing a patterning process on the stack structure, so as to form the MIM capacitor comprising alternately stacked electrodes and insulating layers. Performing the patterning process includes: performing a first etching process to remove a first portion of the stack structure exposed by the mask layer; performing a first trimming process on the mask layer to remove a portion of the mask layer, and a first trimmed mask layer is formed; and performing a second etching process to remove a second portion of the stack structure exposed by the first trimmed mask layer.