MIM Capacitor Fabrication via Spacer Isolation and Two-Step Etching
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Solution Overview
Problem
Conventional methods for fabricating metal-insulator-metal (MIM) capacitors often result in electrical shorts due to polymer or conductive residues between the upper and lower electrodes or neighboring metal lines, leading to leakage currents and increased resistance in via contacts.
Innovation Solution
The solution involves forming a hard mask pattern over the upper electrode, removing the photoresist pattern before etching, and using a two-step etch process to ensure uniformity in the remaining dielectric layer thickness, along with forming an isolation layer as a spacer to electrically isolate the electrodes and prevent residue generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photoresist pattern is used during etching process, then etching can be performed, but polymer residues are generated causing electrical shorts
Solution Approach 1:
A spacer layer is introduced as an intermediary component between the upper and lower electrodes. This spacer physically separates the electrodes and prevents polymer residues from causing electrical shorts, while allowing the photoresist-based etching process to proceed normally.
Solution Approach 2:
The spacer layer is formed in advance before the etching process that generates polymer residues. By establishing this protective barrier beforehand, the design prevents the harmful effect of polymer accumulation without requiring changes to the etching process itself.
2Device complexity
If dielectric layer is etched to form patterns, then capacitor structure is created, but thickness uniformity deteriorates
Solution Approach 1:
The dielectric layer processing is divided into multiple etching steps with different selectivities. The first etch forms the basic capacitor structure, while the second etch with adjusted parameters refines the thickness uniformity, separating the structural formation from the precision thickness control.
Solution Approach 2:
Etching parameters such as gas flow rates, power, and chemistry are changed between different etching steps to achieve different selectivities. This allows the process to first create the required capacitor structure and then fine-tune the dielectric thickness uniformity.
3Manufacturing precision
If multiple etching steps are performed, then capacitor structure is formed, but fabrication time increases
Solution Approach 1:
Multiple etching operations are combined into a single integrated process flow where the spacer formation and electrode patterning are performed in sequence without breaking the vacuum or requiring separate tool transfers. This reduces overall fabrication time while maintaining the precision of multiple etching steps.
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E~2A
AI summary
A capacitor includes a lower electrode (303); a dielectric layer (304A) formed on a predetermined portion of the lower electrode; an upper electrode (305A) formed on the dielectric layer; a hard mask pattern (306A) formed on the upper electrode; and an isolation layer (307A) having a shape of a spacer, formed on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer.