MIM Capacitor TiW Bottom Plate Dielectric Thickness Control
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Solution Overview
Problem
Conventional integrated circuit capacitor structures face challenges due to variations in dielectric thickness caused by polysilicon pattern densities, leading to residual dielectric films and potential damage to the polysilicon surface, resulting in lower breakdown voltage.
Innovation Solution
A method is introduced to fabricate a metal-insulator-metal (MIM) capacitor using TiW as the bottom plate and Ti/TiN as the top plate, where a capacitor mask defines the TiW film, and a multilayer dielectric oxide film is etched, followed by deposition of a Ti/TiN liner stack and Tungsten filling, with planarization using CMP or etch-back, avoiding pattern density-dependent CMP variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon is used as the capacitor bottom plate with conventional etching, then the capacitor structure can be formed, but variations in dielectric thickness cause residual dielectric film or damage to the polysilicon surface, reducing breakdown voltage
Solution Approach 1:
The patent changes the material parameter of the bottom plate from polysilicon to TiW (titanium tungsten), which has different etch selectivity characteristics. This material substitution enables better control of the dielectric etching process, eliminating the residual dielectric film and polysilicon damage issues that plagued the polysilicon-based approach.
2Manufacturing precision
If TiW is used as the capacitor bottom plate, then the capacitor etch process becomes more robust with controlled dielectric thickness, but additional process steps are required compared to conventional polysilicon structures
Solution Approach 1:
The TiW layer serves multiple functions: it acts as the capacitor bottom plate, provides an etch stop layer to prevent over-etching of the dielectric, and serves as a diffusion barrier. This multi-functionality consolidates several roles into one material layer, reducing overall process complexity despite the material change.
Solution Approach 2:
The TiW layer acts as an intermediary between the dielectric and the underlying substrate, providing an etch stop function that mediates the etching process. This intermediary layer allows precise control of dielectric thickness removal while protecting the underlying structures, simplifying the overall process control.
3Adaptability or versatility
If polysilicon pattern densities vary across different integrated circuit architectures, then different step height differences occur in the overlying dielectric material, making CMP highly pattern density dependent
Solution Approach 1:
The patent changes the bottom plate material from polysilicon to TiW, which fundamentally alters the CMP behavior. TiW provides a more uniform CMP removal rate that is less sensitive to pattern density variations, thereby decoupling the CMP process from circuit architecture-specific variations and achieving better thickness uniformity across different designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more robust capacitor etch process with controlled dielectric thickness, improved reliability, and reduced substrate coupling, enhancing signal-to-noise ratio without adding mask steps to existing processes.
Implementation Method 1
a Ti/TiN liner stack is deposited
Implementation Method 2
Tungsten is deposited to fill the vias
Implementation Method 3
A planarization process for the Tungsten is then applied using either CMP or etch-back
Data Source
AI summary
In a method of forming MIM capacitor structure, a TiW layer is formed and a capacitor mask is used to define areas of the TiW layer that will be sued in the formation of the MIM capacitor. A capacitor mask is then used to expose surface areas of the TiW layer, followed by deposition of a capacitor dielectric layer. A via mask and etch are then performed to provide a contact via to the bottom plate TiW layer. After the via etch, a Ti/TiN liner stack is deposited. The Ti/TiN multilayer stacked film serves as the capacitor top plate as well as the via contact liner film. Next, Tungsten is deposited to fill the vias and a Tungsten planarization step is performed.