MIM Capacitor Array Layout Under UBM for Packaging Stress
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Solution Overview
Problem
Integrated chips face increased likelihood of MIM capacitor damage during dicing and packaging due to their placement near the seal ring or under the UBM layer, which can lead to reduced capacitance as the chip size decreases, leaving insufficient space for adequate spacing.
Innovation Solution
A MIM array is arranged along the perimeter of the integrated chip, comprising multiple MIM capacitors with reduced areas, coupled in parallel and positioned under the UBM layer and adjacent to the seal ring, allowing them to withstand higher stress and reducing the risk of damage during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If MIM capacitors are placed near the seal ring or under the UBM layer to optimize chip area, then chip area utilization is improved, but the likelihood of capacitor damage during dicing and packaging increases
Solution Approach 1:
The patent divides the capacitor structure into multiple segments by creating an array of smaller MIM capacitors instead of using a single large capacitor. This segmentation allows the capacitors to be arranged in a grid pattern that optimizes space utilization while reducing individual capacitor size and stress concentration, thereby maintaining reliability despite proximity to the seal ring.
Solution Approach 2:
The patent applies different spacing requirements to different regions of the chip. MIM capacitors located near the seal ring are given larger lateral spacing compared to those in the center region. This local quality approach allows optimal space utilization in safe zones while providing enhanced protection to capacitors in high-stress zones near the perimeter.
2Productivity
If chip size is reduced to meet miniaturization demands, then productivity and integration density are improved, but capacitance is reduced due to insufficient spacing
Solution Approach 1:
The patent transitions from two-dimensional capacitor arrangement to three-dimensional stacking by placing multiple MIM capacitor arrays at different vertical levels within the BEOL structure. This dimensional change allows significant capacitance increase within the same chip footprint, enabling miniaturization while maintaining or enhancing total capacitance through vertical space utilization.
Solution Approach 2:
The patent merges multiple small MIM capacitors into a unified capacitor array system that functions as a single equivalent capacitor with higher total capacitance. By combining numerous individual capacitors in parallel configurations across multiple layers, the system achieves the required total capacitance value while occupying minimal chip area, thus resolving the contradiction between chip size reduction and capacitance maintenance.
3Area of stationary object
If MIM capacitors are positioned under the UBM layer to maximize space usage, then area efficiency is improved, but stress during packaging increases leading to potential damage
Solution Approach 1:
The patent segments the capacitor array into multiple small units distributed under the UBM layer rather than placing a single large capacitor. This segmentation reduces the stress footprint on any single location during packaging processes, allowing efficient space utilization while minimizing localized stress concentration that could lead to damage.
Solution Approach 2:
The patent modifies the lateral spacing parameter for MIM capacitors based on their distance from the seal ring. Capacitors near the perimeter are assigned larger spacing values to withstand higher packaging stress, while those in the chip center can have tighter spacing. This parameter adjustment maintains area efficiency while adapting to local stress conditions.
Data Source
AI summary
An integrated chip including a substrate and a transistor device along the substrate. A plurality of conductive interconnects are over the transistor device. A first under-bump metal (UBM) layer is over the conductive interconnects. A first metal bump is directly over the first UBM layer. A metal-insulator-metal (MIM) capacitor array is over the transistor device and under the first UBM layer. The MIM capacitor array includes a first MIM capacitor and a second MIM capacitor coupled in parallel and disposed directly under the first UBM layer.