MIM Capacitor Integration with Vertical FET Fabrication
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Solution Overview
Problem
Conventional semiconductor fabrication techniques for MIM capacitors are time-consuming and costly due to multiple lithographic masking steps, and they occupy a large footprint, making them unsuitable for highly-integrated advanced semiconductor chip applications.
Innovation Solution
The integration of MIM capacitor devices with vertical FET devices within a semiconductor process flow, where the MIM capacitors are fabricated using a method that concurrently forms gate and capacitor electrodes from the same layers of conductive material and dielectric layers, allowing for a compact, high-capacitance design within the FEOL process modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional CMOS fabrication techniques are used for planar MIM capacitors, then the capacitors can be formed with standard process modules, but multiple lithographic masking steps are required which increases fabrication time and cost
Solution Approach 1:
The patent combines the formation of gate electrodes and capacitor electrodes into a single lithographic masking step. The gate electrode pattern and capacitor electrode pattern are formed simultaneously using one photolithography process, eliminating the need for separate masking steps that would otherwise be required for each electrode structure.
Solution Approach 2:
The patent employs a universal lithographic mask pattern that serves dual purposes: defining both the gate electrode regions for vertical FET devices and the capacitor electrode regions for MIM capacitors. This single mask pattern performs multiple functions that traditionally would require separate patterning operations.
2Ease of manufacture
If conventional CMOS fabrication techniques are used for planar MIM capacitors, then the capacitors can be formed with standard process modules, but the complexity of additional processing steps increases
Solution Approach 1:
The patent merges the capacitor formation process with the vertical FET fabrication process. The same gate dielectric layer, gate electrode layer, and subsequent processing steps serve both the FET gate structures and the MIM capacitor structures, reducing the overall number of discrete processing steps.
Solution Approach 2:
The patent segments the substrate into different device regions (first device region for vertical FETs, second device region for MIM capacitors) that can be processed simultaneously using the same process modules. This segmentation allows different device types to be formed in parallel without requiring separate processing sequences.
3Productivity
If planar MIM capacitor structures are used, then the capacitors can be formed with conventional processes, but they occupy a relatively large footprint of die area
Solution Approach 1:
The patent transitions from planar (2D) capacitor electrode arrangement to a vertical (3D) configuration where capacitor electrodes are formed extending through multiple layers and device regions. This dimensional change allows the capacitor structure to utilize the vertical dimension for capacitance accumulation, reducing the horizontal footprint on the die surface.
Solution Approach 2:
The patent nests the MIM capacitor structure within the same layer structure as the vertical FET devices. The capacitor electrodes are formed using the same gate dielectric and gate electrode layers that define the FET gates, effectively nesting the capacitor functionality within the existing device architecture rather than requiring separate dedicated capacitor regions.
Data Source
AI summary
Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.