MIM Capacitor Vertical Stack Over Top Metal Layer
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitors formed in interconnect structures face issues with parasitic capacitance affecting their capacitance values due to the integration with copper lines and vias, limiting the routing of metal lines under and overlapping the capacitors.
Innovation Solution
A novel integrated circuit structure is developed where a top metal layer has an Ultra-Thick Metal (UTM) layer disposed over it, with a MIM capacitor positioned under the UTM layer and over the top metal layer, eliminating the need for additional metal layers and reducing parasitic capacitance without hindering metal line routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If MIM capacitors are formed at the same level as via layers connecting overlying and underlying metal layers, then the capacitor structure is integrated with the interconnect structure, but no metal line can be routed in the metal layer immediately under the MIM capacitors and in the regions vertically overlapping the MIM capacitors due to parasitic capacitance effects
Solution Approach 1:
The patent moves the MIM capacitor from the conventional planar location (at the same level as via layers) to a vertical stack configuration where the capacitor is positioned between the top metal layer and the UTM layer. This dimensional repositioning allows metal lines to be routed in the metal layer below the capacitor without creating parasitic capacitance, as the capacitor no longer overlaps vertically with the signal routing layer.
2Ease of manufacture
If MIM capacitors are formed at the same level as via layers, then integration with damascene processes is achieved, but parasitic capacitors between MIM capacitors and nearby metal lines adversely affect capacitance values
Solution Approach 1:
The patent resolves the parasitic capacitance issue by repositioning the MIM capacitor in the vertical dimension. The capacitor is formed between the top metal layer and the UTM layer, creating a stack structure where the capacitor electrodes are separated from signal routing metal lines by at least one complete metal layer thickness. This spatial separation eliminates the parasitic capacitance coupling between the MIM capacitor and nearby metal lines, ensuring accurate capacitance values while maintaining integration with the interconnect structure.
3Ease of operation
If additional metal layers are added to allow routing under MIM capacitors, then metal line routing flexibility is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent utilizes the existing UTM (Ultra-Thick Metal) layer, which was originally intended for other purposes, to serve a dual function: as a structural element of the MIM capacitor (forming the top electrode) and as a shielding layer that enables metal line routing in the underlying metal layers. This multi-functional use of the UTM layer eliminates the need for additional dedicated metal layers solely for routing purposes, maintaining routing flexibility while avoiding increased device complexity.
Data Source
AI summary
A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.