MIM Capacitor Contact Layout for Balanced Via Etching
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Solution Overview
Problem
Existing Metal-Insulator-Metal (MIM) capacitors face issues with over-etching of lower contact features under larger contact vias, leading to defects and reduced reliability due to varying sizes of contact vias in different device regions.
Innovation Solution
Incorporating additional conductive features in regions with larger contact vias to balance etching rates, reducing the extent of over-etching by providing one more conductive feature in areas with larger contact vias, thereby minimizing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If contact vias of varying sizes are used in different device regions, then device functionality is improved, but over-etching of lower contact features occurs leading to defects
Solution Approach 1:
The patent applies local quality by forming different numbers of conductive features in different device regions. Specifically, a first number of conductive features is formed in a first device region while a second number of conductive features is formed in a second device region, where the first number differs from the second number. This local variation compensates for varying etching rates caused by different via sizes, preventing over-etching in regions with larger contact vias while maintaining device functionality.
2Reliability
If additional conductive features are added to balance etching rates, then over-etching is reduced, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the conductive features before the contact via etching process. The conductive features are prepared in advance with region-specific quantities, so that when etching occurs, the etching rates are automatically balanced without requiring real-time adjustments. This preliminary configuration prevents over-etching while managing device complexity through systematic pre-planning.
Data Source
AI summary
Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.