BEOL MIM Capacitor Structure for Via Formation Without Plate Etch Stops
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Solution Overview
Problem
Existing Metal-Insulator-Metal (MIM) capacitors in semiconductor integrated circuits face challenges in the complexity of their fabrication process, particularly in forming contact vias, which often require etch stop layers on conductor plate layers, complicating the process and potentially increasing parasitic capacitance.
Innovation Solution
A method is introduced where a device structure includes a lower contact feature in a first dielectric layer with an etch stop layer, a MIM capacitor formed over the etch stop layer, and a contact via extending through both the second dielectric layer and the MIM capacitor, simplifying the fabrication process by eliminating the need for etch stop layers on conductor plate layers and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If etch stop layers are added on conductor plate layers to facilitate contact via formation, then contact via formation becomes easier, but device structure complexity increases and parasitic capacitance increases
Solution Approach 1:
The patent removes the etch stop layer from the conductor plate structure, extracting the problematic element that was causing increased complexity and parasitic capacitance. The contact via is formed directly through the insulator layer and conductor plate without requiring an additional etch stop layer, thus simplifying the overall structure while maintaining manufacturability.
Solution Approach 2:
The patent segments the etch stop function from the conductor plate structure by placing the etch stop layer in the interconnect structure rather than on the conductor plate. This separation allows the contact via formation process to work effectively without adding complexity to the capacitor structure.
2Ease of manufacture
If etch stop layers are added on conductor plate layers to facilitate contact via formation, then contact via formation becomes easier, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the etch stop layer from the conductor plate structure, removing the source of parasitic capacitance. By forming the contact via directly through the insulator layer and conductor plate without an intermediate etch stop layer, the harmful parasitic capacitance is eliminated while the contact via formation process remains effective.
3Device complexity
If fabrication process steps are simplified by eliminating etch stop layers on conductor plates, then manufacturing complexity decreases, but contact via formation difficulty increases
Solution Approach 1:
The patent introduces the insulator layer as an intermediary that facilitates contact via formation without requiring an etch stop layer on the conductor plate. The contact via penetrates through the insulator layer and makes contact with the conductor plate, using the insulator layer as a natural etch stop that simplifies the overall process.
Data Source
AI summary
Back-end-of-line (BEOL) passive device structures and methods of forming the same are provided. In an embodiment, a semiconductor structure includes a first lower contact feature in a first dielectric layer, an etch stop layer on the first dielectric layer, a metal-insulator-metal (MIM) capacitor formed over the etch stop layer, a second dielectric layer over the MIM capacitor, a first contact via extending through both the second dielectric layer and the MIM capacitor and electrically coupled to the first lower contact feature, and a first upper contact feature over and electrically coupled to the first contact via, where a bottom plate of the MIM capacitor is in direct contact with the etch stop layer.