MIM Capacitor Via Integration in Integrated Chip Fabrication
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Solution Overview
Problem
The integration of MIM capacitors within the back-end-of-the-line metallization stack in integrated chips poses fabrication challenges due to topography issues and potential electrical shorting, which complicates the formation of vias and increases the complexity of chip fabrication.
Innovation Solution
The MIM capacitor is positioned within a capacitor inter-level dielectric layer, with a dielectric buffer layer separating it from the under-metal layer to prevent hillocks and parasitic capacitance, and a plurality of vias are used to provide vertical connections to both the MIM capacitor and the under-metal layer, eliminating the need for specifically designated vias for the MIM capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the MIM capacitor is integrated within the back-end-of-the-line metallization stack, then the chip functionality is enhanced with passive devices, but topography issues and potential electrical shorting occur which complicate via formation
Solution Approach 1:
The patent divides the capacitor structure into distinct segments: the MIM capacitor is separated from the under-metal layer by a dielectric buffer layer. This segmentation isolates the capacitor components, preventing electrical shorting while maintaining functional integration within the metallization stack.
Solution Approach 2:
A dielectric buffer layer is introduced as an intermediary element between the MIM capacitor and the under-metal layer. This intermediary prevents direct electrical contact that would cause shorting, while also providing mechanical support and enabling via formation through the capacitor structure.
2Reliability
If specifically designated vias are created for the MIM capacitor, then electrical connection to the capacitor is achieved, but the fabrication process complexity increases
Solution Approach 1:
The via structure is designed to serve multiple functions simultaneously: it provides electrical connection to the MIM capacitor, maintains structural integrity through the dielectric buffer layer, and integrates with the existing metallization stack. This multi-functionality eliminates the need for specially designated vias, simplifying the fabrication process.
Solution Approach 2:
The patent merges the via formation process with the existing metallization stack fabrication. The vias are integrated into the standard interconnect formation process rather than being created as separate, specialized structures, thereby reducing fabrication complexity while ensuring reliable electrical connection.
3Area of stationary object
If the MIM capacitor is positioned close to the under-metal layer, then area is saved, but hillocks and parasitic capacitance are generated
Solution Approach 1:
The dielectric buffer layer acts as an intermediary that physically separates the MIM capacitor from the under-metal layer. This separation prevents the formation of parasitic capacitance between these structures while minimizing the additional area required, as the buffer layer can be made sufficiently thin to perform its electrical isolation function without excessive thickness.
Solution Approach 2:
The dielectric buffer layer provides localized electrical isolation precisely where needed - between the MIM capacitor and under-metal layer - while allowing other areas of the chip to maintain their standard metallization structure. This localized approach to preventing parasitic capacitance optimizes area utilization.
Data Source
AI summary
The present disclosure relates to an integrated chip having a MIM (metal-insulator-metal) capacitor and an associated method of formation. In some embodiments, the integrated chip has a MIM capacitor disposed within a capacitor inter-level dielectric (ILD) layer. An under-metal layer is disposed below the capacitor ILD layer and includes one or more metal structures located under the MIM capacitor. A plurality of vias vertically extend through the capacitor ILD layer and the MIM capacitor. The plurality of vias provide for an electrical connection to the MIM capacitor and to the under-metal layer. By using the plurality of vias to provide for vertical connections to the MIM capacitor and to the under-metal layer, the integrated chip does not use vias that are specifically designated for the MIM capacitor, thereby decreasing the complexity of the integrated chip fabrication.