MIM Capacitor Via Filling with Segmented ONON Stack
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Solution Overview
Problem
The integration of metal-insulator-metal (MIM) capacitors in semiconductor structures faces challenges due to the formation of voids or cracks in connecting vias, which can lead to electrical connection issues and further corrosion problems during pin hole tests, particularly due to the high aspect ratio of the via openings and the use of thick passivation layers.
Innovation Solution
A method for forming a semiconductor structure that includes a MIM capacitor, where a via opening is created through an insulating layer, filled with a conductive layer, and then planarized to form a connecting via, followed by the deposition of additional conductive layers to ensure evenness and prevent overhangs, and an insulating stack is formed to mitigate stress and prevent cracks, using a specific ONON stack configuration of silicon oxide and silicon nitride layers to provide mechanical strength and buffer against external stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If thick passivation layers are used to provide mechanical strength and stress resistance, then the structural integrity is improved, but the aspect ratio of via openings increases leading to voids and cracks
Solution Approach 1:
The patent divides the thick passivation layer into multiple thinner layers (first passivation layer, second passivation layer, third passivation layer) separated by intermediate layers. This segmentation reduces the aspect ratio of individual via openings while maintaining the overall mechanical strength and stress resistance of the complete passivation structure.
Solution Approach 2:
The patent introduces intermediate layers between the passivation layers, creating a multi-dimensional layered structure. This dimensional approach allows the via openings to be filled more effectively by providing additional pathways and reducing the continuous thickness that causes high aspect ratio problems.
2Reliability
If via openings with high aspect ratio are formed through thick passivation layers, then the electrical connection is achieved, but voids and cracks form during filling
Solution Approach 1:
The thick passivation layer is segmented into multiple thinner layers, which directly reduces the aspect ratio of each via opening. This segmentation enables complete and void-free filling of vias while maintaining electrical connection reliability through the continuous conductive paths established in each layer.
Solution Approach 2:
The patent forms the segmented passivation layer structure before creating the via openings. This preliminary action of dividing the passivation layer ensures that subsequent via filling operations encounter reduced aspect ratios, preventing void and crack formation while ensuring reliable electrical connections.
3Reliability
If multiple conductive layers are deposited to ensure evenness and prevent overhangs, then the manufacturing complexity increases, but the connection reliability improves
Solution Approach 1:
The passivation structure is segmented into multiple layers, which naturally creates multiple deposition stages for conductive materials. This segmentation enables even distribution of conductive layers without excessive overhangs, improving connection reliability while the modular nature of the segmentation keeps the overall process manageable.
Solution Approach 2:
The patent applies conductive layers in multiple partial deposits rather than attempting to form complete connections in single thick layers. This partial action approach ensures even coverage and prevents overhang formation, with each layer contributing incrementally to the overall connection reliability.
Data Source
AI summary
A semiconductor structure includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad. The ONON stack includes a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer upwardly disposed over the first insulating layer. A thickness of the second silicon nitride layer is greater than a thickness of the second silicon oxide layer and greater than a thickness of the first silicon nitride layer.