MIM Capacitor Via Spacing for Leakage Reduction
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Solution Overview
Problem
MIM capacitor leakage occurs due to charge diffusion during plasma-based etching, caused by overetching and increased via density, which damages the capacitor plates and reduces capacitance values in semiconductor integrated circuits.
Innovation Solution
Reducing via density by ensuring a spacing between vias and adjacent structures greater than the minimum via spacing requirement of foundry design rules to minimize damage and leakage during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via density is increased to maximize current flow between capacitor plates and contact plates, then electrical connection is improved, but charge diffusion and leakage current increase during plasma etching
Solution Approach 1:
The patent changes the physical parameters of the via structure by increasing via diameter and reducing via density. This modifies the etching process parameters, reducing charge diffusion during plasma etching while maintaining adequate electrical connection through optimized via dimensions and spacing.
Solution Approach 2:
The patent applies different via configurations in different regions of the capacitor structure. Larger vias are used near capacitor plates where charge diffusion is most problematic, while standard vias are used in less critical areas, optimizing both electrical connection and leakage reduction locally.
2Reliability
If via etching is performed to maximum depth to ensure contact with capacitor plates, then connection reliability is improved, but capacitor plate damage and overetching occur
Solution Approach 1:
The patent places a protective layer or cushioning structure above the capacitor plates before via etching. This protective layer prevents direct plasma contact with the capacitor plates during etching, preventing damage and overetching while still allowing the etch to reach the required depth for reliable connection.
Solution Approach 2:
The patent introduces an intermediary protective layer between the plasma etching process and the capacitor plates. This intermediary layer absorbs the harsh etching conditions, protecting the capacitor plates from damage while enabling complete via formation for reliable electrical connection.
3Productivity
If minimum via spacing is used to maximize via density, then current flow is maximized, but leakage current and charge diffusion increase
Solution Approach 1:
The patent changes the spacing parameter from minimum allowed spacing to increased spacing between vias. This parameter change reduces the cumulative charge diffusion effect during plasma etching, lowering leakage current while maintaining adequate current flow through optimized via dimensions and strategic placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the likelihood of capacitor plate damage and charge diffusion, leading to lower leakage current and more reliable, predictable MIM capacitor performance in semiconductor ICs.
Implementation Method 1
the etching process is typically a plasma based process
Implementation Method 2
charge carriers may in fact be diffused through the top capacitor plate into the dielectric while etching, resulting in current leakage
Implementation Method 3
spinning photoresist onto the isolation layer 230 which protects the capacitor, and exposing and developing the photoresist to result in a pattern of exposed holes
Implementation Method 4
the vias 240 can be deposited, typically through chemical vapor deposition (CVD), from which the metal contact layer 210 can now be placed in contact with the vias 240
Data Source
AI summary
A method for reducing leakage current in a semiconductor capacitor. The method includes providing a top plate for collecting charge, providing a bottom plate for collecting an opposing charge to the top plate, providing a dielectric layer for insulation between the top plate and the bottom plate, providing a top contact, providing a bottom contact, providing a plurality of vias including top level vias for connecting the top plate to the top contact, and bottom level vias for connecting the bottom plate to the bottom contact; and separating a via and an adjacent structure such that their distance is greater than a minimum via spacing requirement of a foundry design rule for a semiconductor process producing the semiconductor capacitor.