MIM Capacitor Layout Optimization via Vertical Via Connections
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Solution Overview
Problem
Prior art metal-insulator-metal (MIM) capacitors occupy larger chip areas due to the lower electrode plate extending beyond the upper electrode plate, resulting in ineffective area that does not contribute to capacitance.
Innovation Solution
A MIM capacitor design with a substrate, conductor layer, dielectric layer, and electrodes where the first capacitor electrode partially overlaps the conductor layer, and via connections are used to connect the electrodes, optimizing the layout to minimize chip area and ensure equal electrode areas, with specific materials like copper damascene, silicon nitride, and titanium nitride layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the lower electrode plate extends beyond the upper electrode plate to ensure proper electrical connection and manufacturing tolerance, then the capacitor structure is more robust and easier to manufacture, but the chip area occupied increases due to ineffective area that does not contribute to capacitance
Solution Approach 1:
The patent utilizes the vertical dimension by forming vias that extend downward from the first electrode plate through the dielectric layer to connect with the conductor layer. This vertical connection approach allows the electrode plates to be aligned more closely in the horizontal plane without compromising electrical connection, thereby reducing the chip area occupied by the capacitor while maintaining manufacturing robustness.
Solution Approach 2:
The conductor layer is embedded within the dielectric layer, and the via structure nests the conductive connection path within the capacitor body. The first electrode plate is positioned to partially overlap with the conductor layer, creating a nested configuration where the effective capacitance-forming area is maximized within the minimal footprint, eliminating the need for excessive horizontal extension of electrodes.
2Area of stationary object
If the first capacitor electrode partially overlaps with the conductor layer to maximize capacitance within minimal area, then the chip area usage is optimized, but the electrical connection and manufacturing alignment become more critical and difficult
Solution Approach 1:
The dielectric layer serves as an intermediary that provides a structured framework for positioning the electrodes and conductor layer. The via structures act as intermediaries that establish reliable electrical connections between the first electrode plate and the conductor layer, accommodating alignment tolerances while enabling the partial overlap configuration that maximizes capacitance density.
Solution Approach 2:
The conductor layer is formed in the dielectric layer before the capacitor electrodes are deposited. The via structures are formed to expose portions of the conductor layer at predetermined locations. This preliminary preparation of connection paths allows subsequent electrode deposition to achieve proper alignment and electrical connection with reduced manufacturing complexity, even with the optimized partial overlap configuration.
Data Source
AI summary
An MIM capacitor includes a semiconductor substrate having a conductor layer thereon, a dielectric layer overlying the semiconductor substrate and the conductor layer, and a first capacitor electrode disposed on the dielectric layer. The first capacitor electrode partially overlaps with the conductor layer when viewed from above. A capacitor dielectric layer is disposed on the first capacitor electrode. A second capacitor electrode is disposed on the capacitor dielectric layer. At least one via is disposed in the dielectric layer and electrically connecting the first capacitor electrode with the conductor layer.