MIM Capacitor Stack Layout for Mixed High- and Low-Voltage Integration
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Solution Overview
Problem
Conventional methods for integrating high and low voltage Metal-Insulator-Metal (MIM) capacitors on a single wafer require multiple mask layers, which are costly and time-consuming.
Innovation Solution
A design where a high voltage MIM capacitor is formed adjacent to a low voltage MIM capacitor, utilizing different via widths and a common insulating layer to allow formation of both capacitors using a single mask, reducing the number of masks needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask layers are used to form high voltage and low voltage MIM capacitors separately, then each capacitor can have its specific characteristics, but the fabrication cost and time increase
Solution Approach 1:
The patent combines the formation of high voltage and low voltage MIM capacitors into a single integrated structure sharing common conductive layers and insulating layers. Multiple capacitors are formed simultaneously using a single mask layer, eliminating the need for separate mask layers for each capacitor type, thereby reducing fabrication time and cost while maintaining distinct voltage ratings through different insulator thicknesses
Solution Approach 2:
The patent applies local quality by varying the thickness of insulating layers at different locations within the same MIM structure. The first insulating layer has a first thickness for high voltage regions, while the second insulating layer has a second thickness for low voltage regions. This localized variation in insulator thickness allows each region to have the appropriate electrical characteristics for its intended voltage rating
2Reliability
If multiple mask layers are used to form high voltage and low voltage MIM capacitors separately, then each capacitor can have its specific characteristics, but the fabrication cost increases
Solution Approach 1:
The patent merges the fabrication processes for high voltage and low voltage capacitors into a single unified process. A single mask layer is used to define both types of capacitors simultaneously, and common conductive and insulating layers are formed once for the entire structure, significantly reducing material costs and process complexity compared to forming each capacitor type separately with dedicated mask layers
Solution Approach 2:
The patent creates a universal MIM capacitor structure that can serve multiple voltage requirements. The common conductive layers and insulating layers form a base structure that can be configured for different voltage ratings by simply varying the insulator thickness in different regions, making the structure multi-functional for both high voltage and low voltage applications
3Productivity
If a single mask is used to form both high voltage and low voltage MIM capacitors, then fabrication cost and time are reduced, but the structure complexity increases
Solution Approach 1:
The patent segments the insulating function into multiple distinct insulating layers with different thicknesses. The first insulating layer with first thickness handles high voltage requirements, while the second insulating layer with second thickness handles low voltage requirements. This segmentation allows a single mask to define both capacitor types while maintaining clear functional separation through layer thickness variation
Data Source
Figure 1A~1B
Figure 2A~2C
Figure 2D~2E
AI summary
An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.