High-Density MIM Capacitors With Suspended Lines
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Solution Overview
Problem
Forming high-density metal-insulator-metal capacitors (MIMCAPs) becomes challenging at 10 nm and below due to limitations in existing technologies, which hinder power stability improvements.
Innovation Solution
The method involves forming a gap in a dielectric layer underneath conducting lines, suspending them over the gap, and depositing a capacitor stack with a metallic-insulator-metallic structure, followed by a passivating dielectric material, to increase capacitance density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MIMCAP formation methods are used, then manufacturing process is simpler, but capacitance density is insufficient for 10 nm and below technologies
Solution Approach 1:
The patent transitions from planar capacitor formation to three-dimensional formation by creating air gaps and suspending conducting lines above the substrate. This vertical dimensionality change enables significantly higher capacitance density by allowing capacitor stacks to extend into the third dimension, achieving 64.8 fF/μm² compared to conventional planar methods.
Solution Approach 2:
The patent implements nested structures by forming capacitor stacks within air gaps and suspending conducting lines above the substrate. The multi-layer capacitor stacks are nested within the three-dimensional space created by the air gap structure, maximizing capacitance within a compact footprint.
2Quantity of substance
If thin stacks covering large areas are used, then capacitance density is improved, but manufacturing becomes infeasible at 10 nm and below
Solution Approach 1:
The patent resolves the manufacturing infeasibility by moving from two-dimensional planar stacks to three-dimensional structures with air gaps. This enables capacitance density improvement through vertical stacking and air gap utilization rather than requiring impractically thin stacks or large area coverage at 10 nm scale.
Solution Approach 2:
The patent changes the physical parameters of the capacitor structure by introducing air gaps and suspending conducting lines, transforming the capacitor geometry from conventional planar to three-dimensional. This parameter change enables manufacturability at 10 nm scale while achieving high capacitance density through the air gap and vertical stacking.
3Reliability
If MIMCAPs are positioned closer to device layers, then power stability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent enables positioning MIMCAPs closer to device layers by utilizing the vertical dimension with air gaps and suspended conducting lines. This three-dimensional positioning allows reduced distance to device layers for improved power stability while the air gap structure provides manufacturing tolerance that mitigates the increased precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances capacitance density, allowing MIMCAPs to be positioned closer to device layers, reducing total capacitance needed for power supply stability and achieving higher capacitance density, such as 64.8 fF/μm² in exemplary embodiments.
Implementation Method 1
Forming the gap includes damaging material in the dielectric layer in a capacitor region with a plasma process and etching the damaged material with a wet etch
Implementation Method 2
etching the damaged material with a wet etch
Implementation Method 3
A capacitor stack is deposited in the gap and on the conducting lines
Implementation Method 4
A passivating dielectric material is deposited in the gap after depositing the capacitor stack
Data Source
AI summary
Capacitors and methods of forming the same include forming a gap in a dielectric layer underneath one or more conducting lines, such that the one or more conducting lines are suspended over the gap. A capacitor stack is deposited in the gap and on the conducting lines. Respective contacts are deposited on the conducting lines and on the capacitor stack.